637 lines
105 KiB
Plaintext
637 lines
105 KiB
Plaintext
#-----------------------------------------------------------
|
|
# Vivado v2023.1 (64-bit)
|
|
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
|
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
|
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
|
|
# Start of session at: Tue Sep 1 10:12:21 2026
|
|
# Process ID: 13756
|
|
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v4
|
|
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3664 D:\Project\spinal_stim\pl\spinal_stim_v4\c64_pro.xpr
|
|
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v4/vivado.log
|
|
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v4\vivado.jou
|
|
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
|
|
#-----------------------------------------------------------
|
|
start_gui
|
|
open_project D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.xpr
|
|
reset_run synth_1
|
|
launch_runs synth_1 -jobs 20
|
|
wait_on_run synth_1
|
|
close_design
|
|
open_run synth_1 -name synth_1
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/in001_out ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list mux_pwr_en_OBUF ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/stop_sample ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
wait_on_run impl_1
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
open_hw_manager
|
|
connect_hw_server -allow_non_jtag
|
|
open_hw_target
|
|
set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
|
|
set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
current_hw_device [get_hw_devices xc7z020_1]
|
|
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
|
|
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/axis_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
launch_simulation
|
|
open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
|
|
source pl_top_tb.tcl
|
|
current_wave_config {pl_top_tb_behav.wcfg}
|
|
add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/clk}} {{/pl_top_tb/DUT/u_eeg_emg_upload/rst_n}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/diff_pkt_data_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/emg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/stop_sample}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_data_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_fifo_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en_dly}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_en_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_data}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/msg_crc}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16_out}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc_vld}}
|
|
restart
|
|
run 1 ms
|
|
add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
|
|
add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
|
|
add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
|
|
add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
|
|
close_hw_manager
|
|
open_hw_manager
|
|
connect_hw_server -allow_non_jtag
|
|
open_hw_target
|
|
set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
|
|
set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
current_hw_device [get_hw_devices xc7z020_1]
|
|
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
|
|
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq8'hXX [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'b0 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'b0 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq8'hXX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
reset_run synth_1
|
|
launch_runs synth_1 -jobs 20
|
|
wait_on_run synth_1
|
|
close_design
|
|
open_run synth_1 -name synth_1
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_rst ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list mux_pwr_en_OBUF ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/stop_sample ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
wait_on_run impl_1
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
|
|
close_sim
|