1215 lines
72 KiB
XML
1215 lines
72 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- Product Version: Vivado v2023.1 (64-bit) -->
|
|
<!-- -->
|
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
|
|
|
<Project Product="Vivado" Version="7" Minor="63" Path="D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.xpr">
|
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
<Configuration>
|
|
<Option Name="Id" Val="d2523b19e2bd4a8b8f2a230b0234692c"/>
|
|
<Option Name="Part" Val="xc7z020clg400-2"/>
|
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
|
|
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
|
|
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
|
|
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
|
|
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
|
|
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
|
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
|
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
|
<Option Name="BoardPart" Val=""/>
|
|
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
|
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
<Option Name="ProjectType" Val="Default"/>
|
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
<Option Name="IPCachePermission" Val="read"/>
|
|
<Option Name="IPCachePermission" Val="write"/>
|
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
|
<Option Name="SimCompileState" Val="TRUE"/>
|
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
<Option Name="EnableBDX" Val="FALSE"/>
|
|
<Option Name="WTXSimLaunchSim" Val="58"/>
|
|
<Option Name="WTModelSimLaunchSim" Val="145"/>
|
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
<Option Name="WTXSimExportSim" Val="53"/>
|
|
<Option Name="WTModelSimExportSim" Val="53"/>
|
|
<Option Name="WTQuestaExportSim" Val="53"/>
|
|
<Option Name="WTIesExportSim" Val="6"/>
|
|
<Option Name="WTVcsExportSim" Val="53"/>
|
|
<Option Name="WTRivieraExportSim" Val="53"/>
|
|
<Option Name="WTActivehdlExportSim" Val="53"/>
|
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
<Option Name="XSimRadix" Val="hex"/>
|
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
<Option Name="SimTypes" Val="rtl"/>
|
|
<Option Name="SimTypes" Val="bfm"/>
|
|
<Option Name="SimTypes" Val="tlm"/>
|
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
|
</Configuration>
|
|
<FileSets Version="1" Minor="31">
|
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PSRCDIR/sources_1/bd/design_a9_1/design_a9_1.bd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xci">
|
|
<Proxy FileSetName="design_a9_1_processing_system7_0_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xci">
|
|
<Proxy FileSetName="design_a9_1_CHANN_EN_2"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.xci">
|
|
<Proxy FileSetName="design_a9_1_axis_data_fifo_1_1"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xci">
|
|
<Proxy FileSetName="design_a9_1_axi_dma_1_1"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xci">
|
|
<Proxy FileSetName="design_a9_1_ZCHECK_SPI_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.xci">
|
|
<Proxy FileSetName="design_a9_1_axis_data_fifo_2_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xci">
|
|
<Proxy FileSetName="design_a9_1_axi_dma_2_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xci">
|
|
<Proxy FileSetName="design_a9_1_STIM_SPI_0"/>
|
|
</CompFileExtendedInfo>
|
|
<CompFileExtendedInfo CompFileName="design_a9_1.bd" FileRelPathName="ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xci">
|
|
<Proxy FileSetName="design_a9_1_CHANN_EN_1"/>
|
|
</CompFileExtendedInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/accel/accel_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_arrange.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/utils/breath_gen.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PGENDIR/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_config.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/eeg_emg_upload.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_upload.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/pl_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/utils/pwm_gen.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/utils/run_time.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_config.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_protocol_intan.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_protocol_ql.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_sort.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/upload/upload_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/c64pro_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_top.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_mon_config.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_ch_map.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/cur_monitor.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/acq_collect.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_if.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/stim_config.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top1.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_spi1.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_if1.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="c64pro_top"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
<Filter Type="Constrs"/>
|
|
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ads1299.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ads1299_emg.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/c64pro_pins_ic.xdc"/>
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/ads1299_mod.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_mod.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/pl_top_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/eeg/eeg_top_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/utils/spi_full_duplex_master_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/rhs2116_top_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/sine_gen_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/led_ctrl_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/trigger/trigger_top_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/switch/channel_switch_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/switch/adg1414_if_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/transmit_config_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/cnv_res_collect_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/rtl/rhs2116/trans_timer_tb.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSIMDIR/pl_top_tb_behav.wcfg">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="pl_top_tb"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="TransportPathDelay" Val="0"/>
|
|
<Option Name="TransportIntDelay" Val="0"/>
|
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
<Option Name="PamDesignTestbench" Val=""/>
|
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
<Option Name="XSimWcfgFile" Val="$PSIMDIR/pl_top_tb_behav.wcfg"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
<Filter Type="Utils"/>
|
|
<Config>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_processing_system7_0_0" RelGenDir="$PGENDIR/design_a9_1_processing_system7_0_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_processing_system7_0_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="axis_data_fifo_w8_d128" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axis_data_fifo_w8_d128" RelGenDir="$PGENDIR/axis_data_fifo_w8_d128">
|
|
<File Path="$PSRCDIR/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="axis_data_fifo_w8_d128"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="fifo_generator_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_generator_0" RelGenDir="$PGENDIR/fifo_generator_0">
|
|
<File Path="$PSRCDIR/sources_1/ip/fifo_generator_0/fifo_generator_0.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="fifo_generator_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_CHANN_EN_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_CHANN_EN_1" RelGenDir="$PGENDIR/design_a9_1_CHANN_EN_1">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_CHANN_EN_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="fifo_generator_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_generator_1" RelGenDir="$PGENDIR/fifo_generator_1">
|
|
<File Path="$PSRCDIR/sources_1/ip/fifo_generator_1/fifo_generator_1.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="fifo_generator_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_cur_flt_state" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_cur_flt_state" RelGenDir="$PGENDIR/vio_cur_flt_state">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_cur_flt_state"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="c_add_s16_s32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/c_add_s16_s32" RelGenDir="$PGENDIR/c_add_s16_s32">
|
|
<File Path="$PSRCDIR/sources_1/ip/c_add_s16_s32/c_add_s16_s32.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="c_add_s16_s32"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_CHANN_EN_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_CHANN_EN_2" RelGenDir="$PGENDIR/design_a9_1_CHANN_EN_2">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_CHANN_EN_2"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_STIM_SPI_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_STIM_SPI_0" RelGenDir="$PGENDIR/design_a9_1_STIM_SPI_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_STIM_SPI_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_ZCHECK_SPI_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_ZCHECK_SPI_0" RelGenDir="$PGENDIR/design_a9_1_ZCHECK_SPI_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_ZCHECK_SPI_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_axis_data_fifo_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_axis_data_fifo_2_0" RelGenDir="$PGENDIR/design_a9_1_axis_data_fifo_2_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_axis_data_fifo_2_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_axi_dma_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_axi_dma_2_0" RelGenDir="$PGENDIR/design_a9_1_axi_dma_2_0">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_axi_dma_2_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_axis_data_fifo_1_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_axis_data_fifo_1_1" RelGenDir="$PGENDIR/design_a9_1_axis_data_fifo_1_1">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_axis_data_fifo_1_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="design_a9_1_axi_dma_1_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_a9_1_axi_dma_1_1" RelGenDir="$PGENDIR/design_a9_1_axi_dma_1_1">
|
|
<Config>
|
|
<Option Name="TopModule" Val="design_a9_1_axi_dma_1_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
<Option Name="CompiledLib" Val="0"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Questa">
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Riviera">
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="ActiveHDL">
|
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="20">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_processing_system7_0_0" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_processing_system7_0_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="axis_data_fifo_w8_d128_synth_1" Type="Ft3:Synth" SrcSet="axis_data_fifo_w8_d128" Part="xc7z020clg400-2" ConstrsSet="axis_data_fifo_w8_d128" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axis_data_fifo_w8_d128_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_data_fifo_w8_d128_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_data_fifo_w8_d128_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_generator_0_synth_1" Type="Ft3:Synth" SrcSet="fifo_generator_0" Part="xc7z020clg400-2" ConstrsSet="fifo_generator_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_generator_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_generator_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_generator_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_CHANN_EN_1_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_CHANN_EN_1" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_CHANN_EN_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_CHANN_EN_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_1_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_generator_1_synth_1" Type="Ft3:Synth" SrcSet="fifo_generator_1" Part="xc7z020clg400-2" ConstrsSet="fifo_generator_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_generator_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_generator_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_generator_1_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_cur_flt_state_synth_1" Type="Ft3:Synth" SrcSet="vio_cur_flt_state" Part="xc7z020clg400-2" ConstrsSet="vio_cur_flt_state" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_cur_flt_state_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_cur_flt_state_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_cur_flt_state_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="c_add_s16_s32_synth_1" Type="Ft3:Synth" SrcSet="c_add_s16_s32" Part="xc7z020clg400-2" ConstrsSet="c_add_s16_s32" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/c_add_s16_s32_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/c_add_s16_s32_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/c_add_s16_s32_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_CHANN_EN_2_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_CHANN_EN_2" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_CHANN_EN_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_CHANN_EN_2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_2_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_STIM_SPI_0_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_STIM_SPI_0" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_STIM_SPI_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_STIM_SPI_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_STIM_SPI_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_STIM_SPI_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_ZCHECK_SPI_0_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_ZCHECK_SPI_0" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_ZCHECK_SPI_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_ZCHECK_SPI_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_ZCHECK_SPI_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_ZCHECK_SPI_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axis_data_fifo_2_0_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_axis_data_fifo_2_0" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axis_data_fifo_2_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_axis_data_fifo_2_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_2_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_2_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axi_dma_2_0_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_axi_dma_2_0" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axi_dma_2_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_axi_dma_2_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_2_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_2_0_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axis_data_fifo_1_1_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_axis_data_fifo_1_1" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axis_data_fifo_1_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_axis_data_fifo_1_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_1_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_1_1_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axi_dma_1_1_synth_1" Type="Ft3:Synth" SrcSet="design_a9_1_axi_dma_1_1" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axi_dma_1_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_a9_1_axi_dma_1_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_1_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_1_1_synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 20 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="impl_1_copy_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design" EnableStepBool="1"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019" CtrlBit="true">
|
|
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="c64pro_top_timing_summary_init_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="c64pro_top_drc_opted_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="c64pro_top_timing_summary_opted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="c64pro_top_timing_summary_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="c64pro_top_io_placed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="c64pro_top_utilization_placed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="c64pro_top_control_sets_placed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="verbose" Type="" Value="true"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="c64pro_top_incremental_reuse_pre_placed.rpt_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="c64pro_top_incremental_reuse_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="c64pro_top_timing_summary_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="c64pro_top_timing_summary_postplace_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="c64pro_top_timing_summary_physopted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="c64pro_top.vdi">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="c64pro_top_drc_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="c64pro_top_methodology_drc_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="c64pro_top_power_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="c64pro_top_route_status_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="c64pro_top_timing_summary_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="c64pro_top_incremental_reuse_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="c64pro_top_clock_utilization_routed_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="c64pro_top_bus_skew_routed_1.rpt" Version="1" Minor="1">
|
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="c64pro_top_timing_summary_postroute_physopted_1.rpt" Version="1" Minor="0">
|
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="c64pro_top_bus_skew_postroute_physopted_1.rpt" Version="1" Minor="1">
|
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="report_webtalk" Name="impl_1_copy_1_bitstream_report_webtalk_0" Spec="" RunStep="write_bitstream" ReportFile="usage_statistics_webtalk.html">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="c64pro_top.vdi">
|
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
|
</ReportConfig>
|
|
</ReportStrategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_processing_system7_0_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="axis_data_fifo_w8_d128_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="axis_data_fifo_w8_d128" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_data_fifo_w8_d128_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_data_fifo_w8_d128_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_data_fifo_w8_d128_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_generator_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="fifo_generator_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_generator_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_generator_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_generator_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_CHANN_EN_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_CHANN_EN_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_CHANN_EN_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_1_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="fifo_generator_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="fifo_generator_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_generator_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_generator_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_generator_1_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_cur_flt_state_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="vio_cur_flt_state" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_cur_flt_state_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_cur_flt_state_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_cur_flt_state_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="c_add_s16_s32_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="c_add_s16_s32" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="c_add_s16_s32_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/c_add_s16_s32_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/c_add_s16_s32_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_CHANN_EN_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_CHANN_EN_2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_CHANN_EN_2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_CHANN_EN_2_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_STIM_SPI_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_STIM_SPI_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_STIM_SPI_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_STIM_SPI_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_STIM_SPI_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_ZCHECK_SPI_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_ZCHECK_SPI_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_ZCHECK_SPI_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_ZCHECK_SPI_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_ZCHECK_SPI_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axis_data_fifo_2_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axis_data_fifo_2_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_axis_data_fifo_2_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_2_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_2_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axi_dma_2_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axi_dma_2_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_axi_dma_2_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_2_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_2_0_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axis_data_fifo_1_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axis_data_fifo_1_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_axis_data_fifo_1_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_1_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axis_data_fifo_1_1_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="design_a9_1_axi_dma_1_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="design_a9_1_axi_dma_1_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_a9_1_axi_dma_1_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_1_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_a9_1_axi_dma_1_1_impl_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
</Runs>
|
|
<Board/>
|
|
<DashboardSummary Version="1" Minor="0">
|
|
<Dashboards>
|
|
<Dashboard Name="default_dashboard">
|
|
<Gadgets>
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
</Gadget>
|
|
</Gadgets>
|
|
</Dashboard>
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
</Dashboards>
|
|
</DashboardSummary>
|
|
</Project>
|