144 lines
15 KiB
Plaintext
144 lines
15 KiB
Plaintext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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