772 lines
90 KiB
Plaintext
772 lines
90 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Sun Aug 4 13:40:39 2024
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# Process ID: 63460
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# Current directory: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1
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# Command line: vivado.exe -log c64pro_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source c64pro_top.tcl -notrace
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# Log file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top.vdi
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# Journal file: D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1\vivado.jou
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# Running On: 840-5CG14025H4, OS: Windows, CPU Frequency: 2803 MHz, CPU Physical cores: 4, Host memory: 34024 MB
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#-----------------------------------------------------------
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source c64pro_top.tcl -notrace
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create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1392.047 ; gain = 159.227
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add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1495.656 ; gain = 64.137
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Command: link_design -top c64pro_top -part xc7z010clg400-2
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Device 21-403] Loading part xc7z010clg400-2
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8.dcp' for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/u_mult_gain'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch.dcp' for cell 'u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32.dcp' for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16.dcp' for cell 'u_pl_top/u_trigger_top/u_trigger_fifo'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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INFO: [Project 1-454] Reading design checkpoint 'd:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.970 . Memory (MB): peak = 2036.340 ; gain = 0.000
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INFO: [Netlist 29-17] Analyzing 2190 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_0/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_0/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_1/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_1/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
INFO: [Project 1-1714] 193 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2859.234 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 122 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 4 instances
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 110 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 7 instances
|
|
|
|
29 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
link_design completed successfully
|
|
link_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2859.234 ; gain = 1363.578
|
|
Command: opt_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
|
Running DRC as a precondition to command opt_design
|
|
|
|
Starting DRC Task
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2859.234 ; gain = 0.000
|
|
|
|
Starting Cache Timing Information Task
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Ending Cache Timing Information Task | Checksum: 29bb6c343
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2859.234 ; gain = 0.000
|
|
|
|
Starting Logic Optimization Task
|
|
|
|
Phase 1 Retarget
|
|
INFO: [Opt 31-1566] Pulled 8 inverters resulting in an inversion of 108 pins
|
|
INFO: [Opt 31-138] Pushed 19 inverter(s) to 104 load pin(s).
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|
Phase 1 Retarget | Checksum: 1e0d313f9
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-389] Phase Retarget created 177 cells and removed 273 cells
|
|
INFO: [Opt 31-1021] In phase Retarget, 284 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 2 Constant propagation
|
|
INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s).
|
|
Phase 2 Constant propagation | Checksum: 2788da6c6
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-389] Phase Constant propagation created 35 cells and removed 213 cells
|
|
INFO: [Opt 31-1021] In phase Constant propagation, 280 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 3 Sweep
|
|
Phase 3 Sweep | Checksum: 1cc33eb61
|
|
|
|
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 643 cells
|
|
INFO: [Opt 31-1021] In phase Sweep, 352 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 4 BUFG optimization
|
|
Phase 4 BUFG optimization | Checksum: 1cc33eb61
|
|
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
|
|
|
Phase 5 Shift Register Optimization
|
|
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
|
Phase 5 Shift Register Optimization | Checksum: 214797f7b
|
|
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
|
|
|
Phase 6 Post Processing Netlist
|
|
Phase 6 Post Processing Netlist | Checksum: 1e8e24ef7
|
|
|
|
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
|
INFO: [Opt 31-1021] In phase Post Processing Netlist, 335 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
Opt_design Change Summary
|
|
=========================
|
|
|
|
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Retarget | 177 | 273 | 284 |
|
|
| Constant propagation | 35 | 213 | 280 |
|
|
| Sweep | 11 | 643 | 352 |
|
|
| BUFG optimization | 0 | 0 | 0 |
|
|
| Shift Register Optimization | 0 | 0 | 0 |
|
|
| Post Processing Netlist | 0 | 0 | 335 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
Starting Connectivity Check Task
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 3187.453 ; gain = 0.000
|
|
Ending Logic Optimization Task | Checksum: 206147d49
|
|
|
|
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3187.453 ; gain = 19.949
|
|
|
|
Starting Power Optimization Task
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running Vector-less Activity Propagation...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
|
|
|
|
Starting PowerOpt Patch Enables Task
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 28 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 4 WE to EN ports
|
|
Number of BRAM Ports augmented: 27 newly gated: 4 Total Ports: 56
|
|
Ending PowerOpt Patch Enables Task | Checksum: 17ad8fe0e
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.290 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Ending Power Optimization Task | Checksum: 17ad8fe0e
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3462.988 ; gain = 275.535
|
|
|
|
Starting Final Cleanup Task
|
|
Ending Final Cleanup Task | Checksum: 17ad8fe0e
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Starting Netlist Obfuscation Task
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Ending Netlist Obfuscation Task | Checksum: 1cbf63ea0
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
56 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
opt_design completed successfully
|
|
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.988 ; gain = 603.754
|
|
INFO: [runtcl-4] Executing : report_drc -file c64pro_top_drc_opted.rpt -pb c64pro_top_drc_opted.pb -rpx c64pro_top_drc_opted.rpx
|
|
Command: report_drc -file c64pro_top_drc_opted.rpt -pb c64pro_top_drc_opted.pb -rpx c64pro_top_drc_opted.rpx
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_drc_opted.rpt.
|
|
report_drc completed successfully
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.166 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_opt.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Command: place_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
Running DRC as a precondition to command place_design
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 25 Warnings
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
Starting Placer Task
|
|
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
|
|
|
Phase 1 Placer Initialization
|
|
|
|
Phase 1.1 Placer Initialization Netlist Sorting
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131a83327
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6625e32b
|
|
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 1.3 Build Placer Netlist Model
|
|
Phase 1.3 Build Placer Netlist Model | Checksum: 1c4ab50df
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 1.4 Constrain Clocks/Macros
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c4ab50df
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 1 Placer Initialization | Checksum: 1c4ab50df
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 2 Global Placement
|
|
|
|
Phase 2.1 Floorplanning
|
|
Phase 2.1 Floorplanning | Checksum: 18862b5c9
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 2.2 Update Timing before SLR Path Opt
|
|
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 168e9c1ca
|
|
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 2.3 Post-Processing in Floorplanning
|
|
Phase 2.3 Post-Processing in Floorplanning | Checksum: 168e9c1ca
|
|
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 2.4 Global Placement Core
|
|
|
|
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
|
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 23300379f
|
|
|
|
Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 2.4.2 Physical Synthesis In Placer
|
|
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 731 LUT instances to create LUTNM shape
|
|
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
|
INFO: [Physopt 32-1138] End 1 Pass. Optimized 286 nets or LUTs. Breaked 0 LUT, combined 286 existing LUTs and moved 0 existing LUT
|
|
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Summary of Physical Synthesis Optimizations
|
|
============================================
|
|
|
|
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
| LUT Combining | 0 | 286 | 286 | 0 | 1 | 00:00:00 |
|
|
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Total | 0 | 286 | 286 | 0 | 4 | 00:00:01 |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 222fb5db7
|
|
|
|
Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 2.4 Global Placement Core | Checksum: 1aab3e1bd
|
|
|
|
Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 2 Global Placement | Checksum: 1aab3e1bd
|
|
|
|
Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3 Detail Placement
|
|
|
|
Phase 3.1 Commit Multi Column Macros
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 220b18073
|
|
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 150d57a78
|
|
|
|
Time (s): cpu = 00:00:25 ; elapsed = 00:00:34 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.3 Area Swap Optimization
|
|
Phase 3.3 Area Swap Optimization | Checksum: 19de4f7a5
|
|
|
|
Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.4 Pipeline Register Optimization
|
|
Phase 3.4 Pipeline Register Optimization | Checksum: 197e3b084
|
|
|
|
Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.5 Small Shape Detail Placement
|
|
Phase 3.5 Small Shape Detail Placement | Checksum: 1949e533e
|
|
|
|
Time (s): cpu = 00:00:32 ; elapsed = 00:00:51 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.6 Re-assign LUT pins
|
|
Phase 3.6 Re-assign LUT pins | Checksum: 1314de745
|
|
|
|
Time (s): cpu = 00:00:33 ; elapsed = 00:00:52 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 3.7 Pipeline Register Optimization
|
|
Phase 3.7 Pipeline Register Optimization | Checksum: 2126447db
|
|
|
|
Time (s): cpu = 00:00:33 ; elapsed = 00:00:52 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 3 Detail Placement | Checksum: 2126447db
|
|
|
|
Time (s): cpu = 00:00:33 ; elapsed = 00:00:52 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|
|
|
Phase 4.1 Post Commit Optimization
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
|
|
Phase 4.1.1 Post Placement Optimization
|
|
Post Placement Optimization Initialization | Checksum: 15ed21199
|
|
|
|
Phase 4.1.1.1 BUFG Insertion
|
|
|
|
Starting Physical Synthesis Task
|
|
|
|
Phase 1 Physical Synthesis Initialization
|
|
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.274 | TNS=0.000 |
|
|
Phase 1 Physical Synthesis Initialization | Checksum: 19032a807
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
INFO: [Place 46-33] Processed net u_ps_a9_1/bbstub_peripheral_aresetn[0], BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
|
Ending Physical Synthesis Task | Checksum: 19032a807
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: 15ed21199
|
|
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:01:02 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 4.1.1.2 Post Placement Timing Optimization
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.612. For the most accurate timing information please run report_timing.
|
|
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: f5651aa4
|
|
|
|
Time (s): cpu = 00:00:39 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Time (s): cpu = 00:00:39 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
Phase 4.1 Post Commit Optimization | Checksum: f5651aa4
|
|
|
|
Time (s): cpu = 00:00:39 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 4.2 Post Placement Cleanup
|
|
Phase 4.2 Post Placement Cleanup | Checksum: f5651aa4
|
|
|
|
Time (s): cpu = 00:00:39 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
|
|
|
|
Phase 4.3 Placer Reporting
|
|
|
|
Phase 4.3.1 Print Estimated Congestion
|
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INFO: [Place 30-612] Post-Placement Estimated Congestion
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____________________________________________________
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| | Global Congestion | Short Congestion |
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| Direction | Region Size | Region Size |
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|___________|___________________|___________________|
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| North| 1x1| 8x8|
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|___________|___________________|___________________|
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| South| 1x1| 4x4|
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|___________|___________________|___________________|
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| East| 1x1| 4x4|
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|___________|___________________|___________________|
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| West| 1x1| 4x4|
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|___________|___________________|___________________|
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Phase 4.3.1 Print Estimated Congestion | Checksum: f5651aa4
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Time (s): cpu = 00:00:40 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Phase 4.3 Placer Reporting | Checksum: f5651aa4
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Time (s): cpu = 00:00:40 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Time (s): cpu = 00:00:40 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: fd983246
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Time (s): cpu = 00:00:40 ; elapsed = 00:01:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Ending Placer Task | Checksum: bf1de071
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Time (s): cpu = 00:00:40 ; elapsed = 00:01:04 . Memory (MB): peak = 3462.988 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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92 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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place_design: Time (s): cpu = 00:00:42 ; elapsed = 00:01:05 . Memory (MB): peak = 3462.988 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_io -file c64pro_top_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 3462.988 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file c64pro_top_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 3462.988 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3462.988 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_placed.dcp' has been generated.
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write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Phase 1 Build RT Design
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Checksum: PlaceDB: 7c9f1e35 ConstDB: 0 ShapeSum: 427ec23c RouteDB: 0
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Post Restoration Checksum: NetGraph: 8316a71c | NumContArr: 13d2371d | Constraints: 190a55ad | Timing: 0
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Phase 1 Build RT Design | Checksum: aff333e6
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Phase 2 Router Initialization
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: aff333e6
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: aff333e6
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Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 3462.988 ; gain = 0.000
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Number of Nodes with overlaps = 0
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Phase 2.3 Update Timing
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Phase 2.3 Update Timing | Checksum: 18a78f2aa
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Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 3485.141 ; gain = 22.152
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.936 | TNS=0.000 | WHS=-0.371 | THS=-778.749|
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.00661599 %
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Global Horizontal Routing Utilization = 0.013557 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 26575
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 26567
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Number of Partially Routed Nets = 8
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Number of Node Overlaps = 3
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Phase 2 Router Initialization | Checksum: 1bd30e870
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Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 3556.641 ; gain = 93.652
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Phase 3 Initial Routing
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Phase 3.1 Global Routing
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Phase 3.1 Global Routing | Checksum: 1bd30e870
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Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 3556.641 ; gain = 93.652
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Phase 3 Initial Routing | Checksum: 23c4c0a48
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Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 3577
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Number of Nodes with overlaps = 519
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Number of Nodes with overlaps = 191
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Number of Nodes with overlaps = 70
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Number of Nodes with overlaps = 37
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Number of Nodes with overlaps = 11
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Number of Nodes with overlaps = 4
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Number of Nodes with overlaps = 0
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.145 | TNS=0.000 | WHS=N/A | THS=N/A |
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Phase 4.1 Global Iteration 0 | Checksum: 19a0c9351
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Time (s): cpu = 00:00:46 ; elapsed = 00:00:58 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 4 Rip-up And Reroute | Checksum: 19a0c9351
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Time (s): cpu = 00:00:46 ; elapsed = 00:00:58 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 5 Delay and Skew Optimization
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Phase 5.1 Delay CleanUp
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Phase 5.1 Delay CleanUp | Checksum: 19a0c9351
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Time (s): cpu = 00:00:46 ; elapsed = 00:00:58 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 5.2 Clock Skew Optimization
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Phase 5.2 Clock Skew Optimization | Checksum: 19a0c9351
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Time (s): cpu = 00:00:46 ; elapsed = 00:00:58 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 5 Delay and Skew Optimization | Checksum: 19a0c9351
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Time (s): cpu = 00:00:46 ; elapsed = 00:00:58 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1.1 Update Timing
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Phase 6.1.1 Update Timing | Checksum: 13145d0ac
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Time (s): cpu = 00:00:47 ; elapsed = 00:01:00 . Memory (MB): peak = 3584.492 ; gain = 121.504
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.145 | TNS=0.000 | WHS=0.036 | THS=0.000 |
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Phase 6.1 Hold Fix Iter | Checksum: 10340c5de
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Time (s): cpu = 00:00:47 ; elapsed = 00:01:00 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 6 Post Hold Fix | Checksum: 10340c5de
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Time (s): cpu = 00:00:47 ; elapsed = 00:01:00 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 18.7362 %
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Global Horizontal Routing Utilization = 25.7424 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Phase 7 Route finalize | Checksum: 1394cc86a
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Time (s): cpu = 00:00:47 ; elapsed = 00:01:00 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: 1394cc86a
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Time (s): cpu = 00:00:47 ; elapsed = 00:01:00 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: bafb349b
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Time (s): cpu = 00:00:49 ; elapsed = 00:01:02 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Phase 10 Post Router Timing
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INFO: [Route 35-57] Estimated Timing Summary | WNS=0.145 | TNS=0.000 | WHS=0.036 | THS=0.000 |
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INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
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Phase 10 Post Router Timing | Checksum: bafb349b
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Time (s): cpu = 00:00:49 ; elapsed = 00:01:03 . Memory (MB): peak = 3584.492 ; gain = 121.504
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INFO: [Route 35-16] Router Completed Successfully
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Phase 11 Post-Route Event Processing
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Phase 11 Post-Route Event Processing | Checksum: 67454976
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Time (s): cpu = 00:00:50 ; elapsed = 00:01:04 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Time (s): cpu = 00:00:50 ; elapsed = 00:01:04 . Memory (MB): peak = 3584.492 ; gain = 121.504
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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109 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:54 ; elapsed = 00:01:06 . Memory (MB): peak = 3584.492 ; gain = 121.504
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INFO: [runtcl-4] Executing : report_drc -file c64pro_top_drc_routed.rpt -pb c64pro_top_drc_routed.pb -rpx c64pro_top_drc_routed.rpx
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Command: report_drc -file c64pro_top_drc_routed.rpt -pb c64pro_top_drc_routed.pb -rpx c64pro_top_drc_routed.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file c64pro_top_methodology_drc_routed.rpt -pb c64pro_top_methodology_drc_routed.pb -rpx c64pro_top_methodology_drc_routed.rpx
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Command: report_methodology -file c64pro_top_methodology_drc_routed.rpt -pb c64pro_top_methodology_drc_routed.pb -rpx c64pro_top_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_methodology_drc_routed.rpt.
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report_methodology completed successfully
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report_methodology: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3681.746 ; gain = 97.254
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INFO: [runtcl-4] Executing : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
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Command: report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
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Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
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119 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
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report_power: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3713.594 ; gain = 31.848
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INFO: [runtcl-4] Executing : report_route_status -file c64pro_top_route_status.rpt -pb c64pro_top_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file c64pro_top_timing_summary_routed.rpt -pb c64pro_top_timing_summary_routed.pb -rpx c64pro_top_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [runtcl-4] Executing : report_incremental_reuse -file c64pro_top_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
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INFO: [runtcl-4] Executing : report_clock_utilization -file c64pro_top_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file c64pro_top_bus_skew_routed.rpt -pb c64pro_top_bus_skew_routed.pb -rpx c64pro_top_bus_skew_routed.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3780.781 ; gain = 47.020
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INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/impl_1/c64pro_top_routed.dcp' has been generated.
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write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3780.781 ; gain = 47.020
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-208] The XPM instance: <u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_ps_a9_1/design_a9_1_i/axis_data_fifo_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_ps_a9_1/design_a9_1_i/axis_data_fifo_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-167] Found XPM memory block u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
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INFO: [Memdata 28-208] The XPM instance: <u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_ps_a9_1/design_a9_1_i/axi_dma_1>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_ps_a9_1/design_a9_1_i/axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-167] Found XPM memory block u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
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INFO: [Memdata 28-208] The XPM instance: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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Command: write_bitstream -force c64pro_top.bit
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command write_bitstream
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/s_axi_cmd_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg has an input control pin u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ENARDEN (net: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclken) which is driven by a register (u_pl_top/u_rhs2116_top/u_sine_wave_gen/aclken_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tvalid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC RTSTAT-10] No routable loads: 55 net(s) have no routable loads. The problem bus(es) and/or net(s) are u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_w_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_ar_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_aw_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_ar_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_b_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_aw_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_b_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_w_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_b_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_w_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_w_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_r_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_b_node/inst/mi_handler_m_sc_areset_pipe, u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_w_node/inst/mi_handler_m_sc_areset_pipe... and (the first 15 of 55 listed).
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INFO: [Vivado 12-3199] DRC finished with 0 Errors, 26 Warnings
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
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INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
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Loading data files...
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Loading site data...
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Loading route data...
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream ./c64pro_top.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
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INFO: [Common 17-83] Releasing license: Implementation
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39 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
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write_bitstream completed successfully
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write_bitstream: Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 4235.977 ; gain = 455.195
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INFO: [Common 17-206] Exiting Vivado at Sun Aug 4 13:45:12 2024...
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