29 lines
591 B
Verilog
29 lines
591 B
Verilog
`timescale 1 ns / 1 ps
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module trigger_detection
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(
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input clk ,
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input rst_n ,
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input [32-1:0] trigger_in ,
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output reg [32-1:0] trigger_tdata ,
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output reg trigger_tvalid
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);
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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trigger_tdata <= 0;
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trigger_tvalid <= 1'b0;
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end else if (trigger_tdata != trigger_in) begin
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trigger_tdata <= trigger_in;
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trigger_tvalid <= 1'b1;
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end else begin
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trigger_tvalid <= 1'b0;
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end
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end
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endmodule
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