`timescale 1 ns / 1 ps

module trigger_detection
	(
		input					clk					,
		input					rst_n				,
		
		input		[32-1:0]	trigger_in			,

		output	reg	[32-1:0]	trigger_tdata	 	,
		output	reg				trigger_tvalid
	);
	
	//*****************************************************************************
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			trigger_tdata <= 0;
			trigger_tvalid <= 1'b0;
		end else if (trigger_tdata != trigger_in) begin
			trigger_tdata <= trigger_in;
			trigger_tvalid <= 1'b1;
		end else begin
			trigger_tvalid <= 1'b0;
		end
	end
	
endmodule