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chunk-sync
2026-09-11 16:18:36 +08:00
parent c315cef09e
commit c2c1bb2648
922 changed files with 102283 additions and 6793 deletions
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c64_pro.srcs/sources_1/rtl/stim_config.v
+119
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`timescale 1 ns / 1 ps
module stim_config#
(
parameter SPIS_QTY = 4 ,
parameter SPI_DATA_WIDTH = 8
)
(
input clk ,
input rst_n ,
(*mark_debug="true"*)input [13-1:0] bram_addr ,
input bram_clk ,
(*mark_debug="true"*)input [32-1:0] bram_din ,
(*mark_debug="true"*)output reg [32-1:0] bram_dout ,
(*mark_debug="true"*)input bram_en ,
input bram_rst ,
(*mark_debug="true"*)input [ 4-1:0] bram_we ,
output reg [1:0] eeg_emg_sel , // eeg_emg_sel[1]:emg,eeg_emg_sel[0]:eeg
output reg [15:0] eeg_send_package_num ,
output reg [15:0] emg_send_package_num ,
(*mark_debug="true"*)output reg diff_pkt_data_sel ,
output reg stop_sample
);
//*****************************************************************************
// localparam definition
//*****************************************************************************
localparam BRAM_ADDR_TEST_RO = 13'h0000;
localparam BRAM_ADDR_TEST_RW = 13'h0004;
localparam BRAM_ADDR_EMG_SEL = 13'h0030;
localparam BRAM_ADDR_EEG_NUM = 13'h0034;
localparam BRAM_ADDR_EMG_NUM = 13'h0038;
localparam BRAM_ADDR_DATA_SEL = 13'h003c;
localparam BRAM_ADDR_STOP_SAMPLE = 13'h0040;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg [32-1:0] test_data ;
(*mark_debug="true"*)wire bram_wr_valid ;
(*mark_debug="true"*)wire bram_rd_valid ;
//write bram/Set config
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n )
test_data <= 0;
else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
test_data <= bram_din;
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
eeg_emg_sel[1:0] <= 2'b0;
end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EMG_SEL ) ) begin
eeg_emg_sel[1:0] <= bram_din[1:0];
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
eeg_send_package_num[15:0] <= 16'b0;
end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EEG_NUM ) ) begin
eeg_send_package_num[15:0] <= bram_din[15:0];
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
emg_send_package_num[15:0] <= 16'b0;
end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EMG_NUM ) ) begin
emg_send_package_num[15:0] <= bram_din[15:0];
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
diff_pkt_data_sel <= 1'b0;
end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_DATA_SEL ) ) begin
diff_pkt_data_sel <= bram_din[0];
end
end
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
stop_sample <= 1'b0;
end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_STOP_SAMPLE ) ) begin
stop_sample <= bram_din[0];
end
end
//read bram/Get config
always @ ( posedge clk or negedge rst_n ) begin
if( !rst_n ) begin
bram_dout <= 0;
end else if ( bram_rd_valid ) begin
if ( bram_addr == BRAM_ADDR_TEST_RO )
bram_dout <= 32'h12345678;
if ( bram_addr == BRAM_ADDR_TEST_RW )
bram_dout <= test_data;
end
end
//*****************************************************************************
// Continuous assignments
//*****************************************************************************
assign bram_wr_valid = bram_en && (bram_we == 4'hF);
assign bram_rd_valid = bram_en && (bram_we == 4'h0);
endmodule