120 lines
3.7 KiB
Verilog
120 lines
3.7 KiB
Verilog
`timescale 1 ns / 1 ps
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module stim_config#
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(
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parameter SPIS_QTY = 4 ,
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parameter SPI_DATA_WIDTH = 8
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)
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(
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input clk ,
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input rst_n ,
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(*mark_debug="true"*)input [13-1:0] bram_addr ,
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input bram_clk ,
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(*mark_debug="true"*)input [32-1:0] bram_din ,
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(*mark_debug="true"*)output reg [32-1:0] bram_dout ,
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(*mark_debug="true"*)input bram_en ,
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input bram_rst ,
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(*mark_debug="true"*)input [ 4-1:0] bram_we ,
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output reg [1:0] eeg_emg_sel , // eeg_emg_sel[1]:emg,eeg_emg_sel[0]:eeg
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output reg [15:0] eeg_send_package_num ,
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output reg [15:0] emg_send_package_num ,
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(*mark_debug="true"*)output reg diff_pkt_data_sel ,
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output reg stop_sample
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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localparam BRAM_ADDR_EMG_SEL = 13'h0030;
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localparam BRAM_ADDR_EEG_NUM = 13'h0034;
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localparam BRAM_ADDR_EMG_NUM = 13'h0038;
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localparam BRAM_ADDR_DATA_SEL = 13'h003c;
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localparam BRAM_ADDR_STOP_SAMPLE = 13'h0040;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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(*mark_debug="true"*)wire bram_wr_valid ;
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(*mark_debug="true"*)wire bram_rd_valid ;
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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test_data <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
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test_data <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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eeg_emg_sel[1:0] <= 2'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EMG_SEL ) ) begin
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eeg_emg_sel[1:0] <= bram_din[1:0];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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eeg_send_package_num[15:0] <= 16'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EEG_NUM ) ) begin
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eeg_send_package_num[15:0] <= bram_din[15:0];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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emg_send_package_num[15:0] <= 16'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EMG_NUM ) ) begin
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emg_send_package_num[15:0] <= bram_din[15:0];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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diff_pkt_data_sel <= 1'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_DATA_SEL ) ) begin
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diff_pkt_data_sel <= bram_din[0];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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stop_sample <= 1'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_STOP_SAMPLE ) ) begin
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stop_sample <= bram_din[0];
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end
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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bram_dout <= 0;
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end else if ( bram_rd_valid ) begin
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if ( bram_addr == BRAM_ADDR_TEST_RO )
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bram_dout <= 32'h12345678;
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if ( bram_addr == BRAM_ADDR_TEST_RW )
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bram_dout <= test_data;
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end
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign bram_wr_valid = bram_en && (bram_we == 4'hF);
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assign bram_rd_valid = bram_en && (bram_we == 4'h0);
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endmodule
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