547 lines
16 KiB
Verilog
547 lines
16 KiB
Verilog
`timescale 1ns/1ps
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module rhs2116_top_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 10; //ns
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parameter CHIPSET_QTY = 4;
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parameter RECORD_DIVISOR = 2-1;
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parameter CMD_CNV = 2'b00;
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parameter CMD_EXTEND = 2'b01;
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parameter CMD_STIM = 2'b01;
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parameter CMD_NULL = 2'b01;
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parameter CMD_END = 2'b01;
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parameter CMD_WRITE = 2'b10;
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parameter CMD_READ = 2'b11;
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parameter STIM_MONITOR_REG_ADDR = 8'd40;
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parameter STIM_POLARITY_REG_ADDR = 8'd44;
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parameter POS_CUR_REG_ADDR = 8'd96;
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parameter NEG_CUR_REG_ADDR = 8'd64;
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localparam BRAM_ADDR_TEST_RW = 13'h0000;
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localparam BRAM_ADDR_TEST_RO_DATA = 13'h0004;
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localparam BRAM_ADDR_TEST_VERSION = 13'h0008;
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localparam BRAM_ADDR_UPDATE_PERIOD = 13'h0020;
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localparam BRAM_ADDR_UPLOAD_ROUND_NUM = 13'h0024;
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localparam BRAM_ADDR_ENABLE = 13'h0028;
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localparam BRAM_ADDR_RESET = 13'h002C;
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localparam BRAM_ADDR_DDS_PHASE_TRIG = 13'h0030;
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localparam BRAM_ADDR_UPLOAD_TIMEOUT = 13'h0048;
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localparam BRAM_ADDR_SPI_STATE_START = 13'h0100;
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localparam BRAM_ADDR_SPI_TX_START = 13'h0180;
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localparam BRAM_ADDR_SPI_RX_START = 13'h0200;
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localparam BRAM_ADDR_SPI_ERR_START = 13'h0280;
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localparam BRAM_ADDR_DDS_PHASE_INC_START = 13'h0400;
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localparam BRAM_ADDR_DDS_PHASE_OFF_START = 13'h0480;
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localparam BRAM_ADDR_CHIP_0_CNV_CMD_LTH = 13'h0500;
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localparam BRAM_ADDR_CHIP_1_CNV_CMD_LTH = 13'h0504;
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localparam BRAM_ADDR_CHIP_2_CNV_CMD_LTH = 13'h0508;
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localparam BRAM_ADDR_CHIP_3_CNV_CMD_LTH = 13'h050C;
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localparam BRAM_ADDR_STIM_TRIM_P_MASK = 13'h1F00;
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localparam BRAM_ADDR_STIM_TRIM_P_START = 13'h0600;
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localparam BRAM_ADDR_STIM_TRIM_N_MASK = 13'h1F00;
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localparam BRAM_ADDR_STIM_TRIM_N_START = 13'h0700;
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localparam BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P = 13'h0600;
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localparam BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_P = 13'h0610;
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localparam BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_P = 13'h0620;
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localparam BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_P = 13'h0630;
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localparam BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N = 13'h0700;
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localparam BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_N = 13'h0710;
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localparam BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_N = 13'h0720;
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localparam BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_N = 13'h0730;
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localparam BRAM_ADDR_CHIP_0_CNV_CMD_START = 13'h1000;
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localparam BRAM_ADDR_CHIP_1_CNV_CMD_START = 13'h1040;
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localparam BRAM_ADDR_CHIP_2_CNV_CMD_START = 13'h1080;
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localparam BRAM_ADDR_CHIP_3_CNV_CMD_START = 13'h10C0;
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localparam CHIP_0 = 4'h0;
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localparam CHIP_1 = 4'h1;
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localparam CHIP_2 = 4'h2;
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localparam CHIP_3 = 4'h3;
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localparam CHANNEL_0 = 0;
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localparam CHANNEL_1 = 1;
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localparam CHANNEL_2 = 2;
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localparam CHANNEL_3 = 3;
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localparam CHANNEL_4 = 4;
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localparam CHANNEL_5 = 5;
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localparam CHANNEL_6 = 6;
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localparam CHANNEL_7 = 7;
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localparam CHANNEL_8 = 8;
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localparam CHANNEL_9 = 9;
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localparam CHANNEL_A = 10;
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localparam CHANNEL_B = 11;
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localparam CHANNEL_C = 12;
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localparam CHANNEL_D = 13;
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localparam CHANNEL_E = 14;
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localparam CHANNEL_F = 15;
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localparam DDS_CH_0 = 0;
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localparam DDS_CH_1 = 1;
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localparam DDS_CH_2 = 2;
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localparam DDS_CH_3 = 3;
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localparam DDS_CH_4 = 4;
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localparam DDS_CH_5 = 5;
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localparam DDS_CH_6 = 6;
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localparam DDS_CH_7 = 7;
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localparam DDS_CH_8 = 8;
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localparam DDS_CH_9 = 9;
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localparam DDS_CH_A = 10;
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localparam DDS_CH_B = 11;
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localparam DDS_CH_C = 12;
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localparam DDS_CH_D = 13;
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localparam DDS_CH_E = 14;
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localparam DDS_CH_F = 15;
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localparam GAIN_MAX = 9'h100;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [13-1:0] bram_addr ;
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// reg bram_clk ;
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reg [32-1:0] bram_din ;
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wire [32-1:0] bram_dout ;
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reg bram_en ;
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reg bram_rst ;
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reg [ 4-1:0] bram_we ;
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wire interrupt ;
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wire [31:0] stim_event_code ;
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//------------------------------------------ FIFO: stim input
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wire [31:0] axi_str_txd_tdata ;
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wire axi_str_txd_tlast ;
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wire axi_str_txd_tready ;
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wire axi_str_txd_tvalid ;
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//------------------------------------------ FIFO: record output
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wire [31:0] axi_str_rxd_tdata ;
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wire axi_str_rxd_tlast ;
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reg axi_str_rxd_tready ;
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wire axi_str_rxd_tvalid ;
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//------------------------------------------ device spi
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wire [CHIPSET_QTY-1:0] cs ;
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wire [CHIPSET_QTY-1:0] sclk ;
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wire [CHIPSET_QTY-1:0] mosi ;
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wire [CHIPSET_QTY-1:0] miso ;
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reg [31:0] s_axis_tdata ;
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reg s_axis_tlast ;
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wire s_axis_tready ;
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reg s_axis_tvalid ;
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wire [31:0] axis_tdata_1 ;
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wire axis_tlast_1 ;
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wire axis_tready_1 ;
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wire axis_tvalid_1 ;
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wire [31:0] axis_tdata_2 ;
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wire axis_tlast_2 ;
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wire axis_tready_2 ;
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wire axis_tvalid_2 ;
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reg start ;
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// integer n;
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// reg [3:0] chip;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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axis_data_fifo_w32_d32 u_axis_stream_data_fifo_1
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(
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.s_axis_aclk ( clk ),
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.s_axis_aresetn ( rst_n ),
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.s_axis_tvalid ( s_axis_tvalid ),
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.s_axis_tready ( s_axis_tready ),
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.s_axis_tdata ( s_axis_tdata ),
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.s_axis_tlast ( s_axis_tlast ),
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.m_axis_tvalid ( axis_tvalid_1 ),
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.m_axis_tready ( axis_tready_1 ),
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.m_axis_tdata ( axis_tdata_1 ),
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.m_axis_tlast ( axis_tlast_1 )
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);
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axis_data_fifo_w32_d32 u_axis_stream_data_fifo_2
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(
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.s_axis_aclk ( clk ),
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.s_axis_aresetn ( rst_n ),
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.s_axis_tvalid ( axis_tvalid_1 ),
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.s_axis_tready ( axis_tready_1 ),
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.s_axis_tdata ( axis_tdata_1 ),
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.s_axis_tlast ( axis_tlast_1 ),
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.m_axis_tvalid ( axis_tvalid_2 ),
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.m_axis_tready ( axis_tready_2 ),
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.m_axis_tdata ( axis_tdata_2 ),
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.m_axis_tlast ( axis_tlast_2 )
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);
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axis_data_fifo_w32_d32 u_axis_stream_data_fifo_3
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(
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.s_axis_aclk ( clk ),
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.s_axis_aresetn ( rst_n ),
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.s_axis_tvalid ( axis_tvalid_2 ),
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.s_axis_tready ( axis_tready_2 ),
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.s_axis_tdata ( axis_tdata_2 ),
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.s_axis_tlast ( axis_tlast_2 ),
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.m_axis_tvalid ( axi_str_txd_tvalid ),
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.m_axis_tready ( axi_str_txd_tready ),
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.m_axis_tdata ( axi_str_txd_tdata ),
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.m_axis_tlast ( axi_str_txd_tlast )
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);
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rhs2116_top#
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(
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.CLK_PERIOD ( T_CLK ),
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.VERSION ( 32'h1000000 ),
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.CHIPSET_QTY ( CHIPSET_QTY ),
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.SPI_CLK_DIV ( 4 ),
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.SPI_TRANS_PERIOD ( 1500 )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_addr ),
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.bram_clk ( 1'b0 ),
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.bram_din ( bram_din ),
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.bram_dout ( bram_dout ),
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.bram_en ( bram_en ),
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.bram_rst ( bram_rst ),
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.bram_we ( bram_we ),
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.interrupt ( interrupt ),
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.stim_event_code ( stim_event_code ),
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//------------------------------------------ FIFO: stim input and record output
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.axi_str_txd_tdata ( axi_str_txd_tdata ),
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.axi_str_txd_tlast ( 1'b0 ),
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.axi_str_txd_tready ( axi_str_txd_tready),
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.axi_str_txd_tvalid ( axi_str_txd_tvalid),
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.axi_str_rxd_tdata ( axi_str_rxd_tdata ),
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.axi_str_rxd_tlast ( axi_str_rxd_tlast ),
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.axi_str_rxd_tready ( axi_str_rxd_tready),
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.axi_str_rxd_tvalid ( axi_str_rxd_tvalid),
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//------------------------------------------ channel stim state
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.sw_enable ( ),
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.sw_data_sel ( ),
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.sw_data_0 ( ),
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.sw_data_1 ( ),
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.sw_state ( 32'h00000000 ),
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//------------------------------------------ device spi
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.stim_en ( ),
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.cs ( cs ),
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.sclk ( sclk ),
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.mosi ( mosi ),
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.miso ( miso ),
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.debug_sig ( )
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);
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generate
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for(i=0; i<CHIPSET_QTY; i=i+1) begin : spi
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rhs2116_mod u_rhs2116_mod
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(
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.cs ( cs[i] ),
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.sclk ( sclk[i] ),
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.mosi ( mosi[i] ),
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.miso ( miso[i] )
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);
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end
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endgenerate
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100
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//Config DDS
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write_bram(BRAM_ADDR_DDS_PHASE_INC_START + 8'h00, 32'h000029F1);
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write_bram(BRAM_ADDR_DDS_PHASE_OFF_START, 32'h0);
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write_bram(BRAM_ADDR_DDS_PHASE_TRIG, 1);
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//Config update period
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write_bram(BRAM_ADDR_UPDATE_PERIOD, 31250/T_CLK);
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#100
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@ ( posedge clk );
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while(1) begin
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// write_fifo(code_cnv (CHIP_0, CHANNEL_0), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_1), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_2), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_3), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_4), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_5), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_6), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_7), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_8), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_9), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_A), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_B), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_C), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_D), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_E), 1'b0);
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// write_fifo(code_cnv (CHIP_0, CHANNEL_F), 1'b0);
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// write_fifo(code_read (CHIP_0, 8'hFB), 1'b0);
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// write_fifo(code_read (CHIP_0, 8'hFC), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_null (CHIP_0), 1'b0);
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write_fifo(code_read (CHIP_0, 8'hFB), 1'b0);
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write_fifo(code_read (CHIP_0, 8'hFC), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_0), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_1), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_2), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_3), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_4), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_5), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_6), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_7), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_8), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_9), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_A), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_B), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_C), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_D), 1'b0);
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write_fifo(code_cnv (CHIP_1, CHANNEL_E), 1'b0);
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write_fifo(code_null (CHIP_1), 1'b0);
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write_fifo(code_read (CHIP_1, 8'hFB), 1'b0);
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write_fifo(code_read (CHIP_1, 8'hFC), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_0), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_1), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_2), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_3), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_4), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_5), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_6), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_7), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_8), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_9), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_A), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_B), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_C), 1'b0);
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write_fifo(code_cnv (CHIP_2, CHANNEL_D), 1'b0);
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write_fifo(code_null (CHIP_2), 1'b0);
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write_fifo(code_null (CHIP_2), 1'b0);
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write_fifo(code_read (CHIP_2, 8'hFB), 1'b0);
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write_fifo(code_read (CHIP_2, 8'hFC), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_0), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_1), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_2), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_3), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_4), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_5), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_6), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_7), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_8), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_9), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_A), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_B), 1'b0);
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write_fifo(code_cnv (CHIP_3, CHANNEL_C), 1'b0);
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write_fifo(code_null (CHIP_3), 1'b0);
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write_fifo(code_null (CHIP_3), 1'b0);
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write_fifo(code_null (CHIP_3), 1'b0);
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write_fifo(code_read (CHIP_3, 8'hFB), 1'b0);
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write_fifo(code_read (CHIP_3, 8'hFC), 1'b0);
|
|
|
|
write_fifo(code_end (0), 1'b1);
|
|
|
|
@ ( posedge clk );
|
|
if (~start) begin
|
|
start <= 1'b1;
|
|
write_bram(BRAM_ADDR_ENABLE, 32'hF);
|
|
end
|
|
end
|
|
|
|
$stop;
|
|
|
|
end
|
|
|
|
//*****************************************************************************
|
|
// Task
|
|
//*****************************************************************************
|
|
task Initial;
|
|
begin
|
|
clk <= 1'b0 ;
|
|
rst_n <= 1'b0 ;
|
|
|
|
|
|
bram_addr <= 0 ;
|
|
bram_din <= 0 ;
|
|
bram_en <= 0 ;
|
|
bram_rst <= 0 ;
|
|
bram_we <= 0 ;
|
|
|
|
s_axis_tdata <= 0 ;
|
|
s_axis_tlast <= 1'b0 ;
|
|
s_axis_tvalid <= 1'b0 ;
|
|
|
|
axi_str_rxd_tready <= 1'b1;
|
|
|
|
start <= 1'b0;
|
|
end
|
|
endtask
|
|
|
|
task write_bram;
|
|
input [12:0] addr;
|
|
input [31:0] data;
|
|
begin
|
|
@ ( posedge clk );
|
|
bram_addr <= addr;
|
|
bram_din <= data;
|
|
bram_en <= 1;
|
|
bram_we <= 4'hF ;
|
|
@ ( posedge clk );
|
|
bram_en <= 0;
|
|
bram_we <= 4'h0;
|
|
end
|
|
endtask
|
|
|
|
task read_bram;
|
|
input [12:0] addr;
|
|
output [31:0] data;
|
|
begin
|
|
@ ( posedge clk );
|
|
bram_addr <= addr;
|
|
bram_en <= 1;
|
|
bram_we <= 4'h0 ;
|
|
@ ( posedge clk );
|
|
bram_en <= 0;
|
|
@ ( posedge clk );
|
|
data <= bram_dout;
|
|
end
|
|
endtask
|
|
|
|
task write_fifo;
|
|
input [32-1:0] tdata;
|
|
input tlast;
|
|
begin
|
|
s_axis_tdata <= tdata;
|
|
s_axis_tvalid <= 1'b1;
|
|
s_axis_tlast <= tlast;
|
|
@ ( posedge clk );
|
|
while(~s_axis_tready) @ ( posedge clk );
|
|
if(tlast) begin
|
|
s_axis_tvalid <= 1'b0;
|
|
s_axis_tlast <= 1'b0;
|
|
end
|
|
end
|
|
endtask
|
|
|
|
function [32:0] code_null;
|
|
input [4-1:0] chip;
|
|
code_null = {CMD_NULL, 2'b00, chip, 24'd0};
|
|
endfunction
|
|
|
|
function [32:0] code_cnv;
|
|
input [4-1:0] chip;
|
|
input [6-1:0] channel;
|
|
code_cnv = {CMD_CNV, 4'd0, chip, channel, 16'd0};
|
|
endfunction
|
|
|
|
function [32:0] code_stim_sine;
|
|
input [4-1:0] chip;
|
|
input [4-1:0] channel;
|
|
input [7-1:0] dds_ch;
|
|
input [9-1:0] gain;
|
|
code_stim_sine = {CMD_STIM, 2'b00, chip, 4'h1, channel, dds_ch, gain};
|
|
endfunction
|
|
|
|
function [32:0] code_stim_sine_cover_cnv;
|
|
input [4-1:0] chip;
|
|
input [4-1:0] channel;
|
|
input [7-1:0] dds_ch;
|
|
input [9-1:0] gain;
|
|
code_stim_sine_cover_cnv = {CMD_STIM, 2'b00, chip, 4'h2, channel, dds_ch, gain};
|
|
endfunction
|
|
|
|
function [32:0] code_write;
|
|
input [ 4-1:0] chip;
|
|
input [ 8-1:0] reg_addr;
|
|
input [16-1:0] data;
|
|
code_write = {CMD_WRITE, 2'b00, chip, reg_addr, data};
|
|
endfunction
|
|
|
|
function [32:0] code_write_u;
|
|
input [ 4-1:0] chip;
|
|
input [ 8-1:0] reg_addr;
|
|
input [16-1:0] data;
|
|
code_write_u = {CMD_WRITE, 2'b10, chip, reg_addr, data};
|
|
endfunction
|
|
|
|
function [32:0] code_read;
|
|
input [ 4-1:0] chip;
|
|
input [ 8-1:0] reg_addr;
|
|
code_read = {CMD_READ, 2'b00, chip, reg_addr, 16'd0};
|
|
endfunction
|
|
|
|
function [32:0] code_read_u;
|
|
input [ 4-1:0] chip;
|
|
input [ 8-1:0] reg_addr;
|
|
code_read_u = {CMD_READ, 2'b10, chip, reg_addr, 16'd0};
|
|
endfunction
|
|
|
|
function [32:0] code_end;
|
|
input [16-1:0] data;
|
|
code_end = {CMD_END, 6'd0, 8'hF0, data};
|
|
endfunction
|
|
|
|
//*****************************************************************************
|
|
// Wire assignment
|
|
//*****************************************************************************
|
|
//
|
|
|
|
endmodule |