224 lines
6.3 KiB
Verilog
224 lines
6.3 KiB
Verilog
`timescale 1 ns / 1 ps
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module channel_switch#
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(
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parameter CLK_PERIOD = 10
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)
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(
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input clk ,
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input rst_n ,
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input enable ,
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input data_sel ,
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input [64-1:0] data_0 ,
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input [64-1:0] data_1 ,
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output [64-1:0] state ,
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output sync ,
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output sclk ,
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output sdin ,
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input sdo
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);
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam IDLE = 4'b0000 ;
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localparam MON_ST = 4'd0001 ;
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localparam CFG_ST = 4'd0011 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [64-1:0] new_data ;
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wire [64-1:0] new_data_map ;
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reg [64-1:0] new_data_r ;
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reg [64-1:0] cur_data ;
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reg [ 4-1:0] cstate ;
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wire s_tready ;
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reg s_tvalid ;
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reg [64-1:0] s_tdata ;
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// wire [64-1:0] probe_out0 ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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adg1414_if#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.CLK_DIV ( 20 ),
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.DATA_WIDTH ( 64 )
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)
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u_adg1414_if
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.s_tready ( s_tready ),
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.s_tvalid ( s_tvalid ),
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.s_tdata ( s_tdata ),
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.sync ( sync ),
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.sclk ( sclk ),
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.sdin ( sdin )
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);
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// vio_0 vio_0_switch
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// (
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// .clk ( clk ), // input wire clk
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// .probe_in0 ( enable ), // input wire [0 : 0] probe_in0
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// .probe_in1 ( data_sel ), // input wire [0 : 0] probe_in1
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// .probe_in2 ( data_0 ), // input wire [63 : 0] probe_in2
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// .probe_in3 ( data_1 ), // input wire [63 : 0] probe_in3
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// .probe_in4 ( new_data ), // input wire [63 : 0] probe_in4
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// .probe_in5 ( state ), // input wire [63 : 0] probe_in5
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// .probe_out0 ( probe_out0 ) // output wire [63 : 0] probe_out0
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// );
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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new_data <= 0;
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else if (!data_sel)
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new_data = data_0;//probe_out0;//
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else
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new_data = data_1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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cstate <= 4'd0;
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end else begin
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case (cstate)
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IDLE:
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if ( enable )
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cstate <= MON_ST;
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else
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cstate <= IDLE;
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MON_ST:
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if ( !enable )
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cstate <= IDLE;
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else if (cur_data != new_data_map)
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cstate <= CFG_ST;
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else
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cstate <= MON_ST;
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CFG_ST:
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if ( s_tvalid && s_tready )
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cstate <= IDLE;
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default:
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cstate <= IDLE;
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endcase
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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new_data_r <= 0;
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else if (enable && cstate == MON_ST)
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new_data_r <= new_data_map;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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s_tvalid <= 1'b0;
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s_tdata <= 0;
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end else if ( s_tvalid && s_tready ) begin
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s_tvalid <= 1'b0;
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end else if ( cstate == CFG_ST ) begin
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s_tvalid <= 1'b1;
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s_tdata <= new_data_r;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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cur_data <= 0;
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end else if ( s_tvalid && s_tready ) begin
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cur_data <= s_tdata;
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end
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign state = cur_data;
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assign new_data_map[ 6] = new_data[ 0];
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assign new_data_map[ 7] = new_data[ 1];
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assign new_data_map[ 5] = new_data[ 2];
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assign new_data_map[ 4] = new_data[ 3];
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assign new_data_map[ 3] = new_data[ 4];
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assign new_data_map[ 2] = new_data[ 5];
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assign new_data_map[ 1] = new_data[ 6];
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assign new_data_map[ 0] = new_data[ 7];
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assign new_data_map[14] = new_data[ 8];
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assign new_data_map[15] = new_data[ 9];
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assign new_data_map[13] = new_data[10];
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assign new_data_map[11] = new_data[11];
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assign new_data_map[ 8] = new_data[12];
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assign new_data_map[10] = new_data[13];
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assign new_data_map[ 9] = new_data[14];
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assign new_data_map[12] = new_data[15];
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assign new_data_map[38] = new_data[16];
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assign new_data_map[39] = new_data[17];
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assign new_data_map[37] = new_data[18];
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assign new_data_map[36] = new_data[19];
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assign new_data_map[35] = new_data[20];
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assign new_data_map[34] = new_data[21];
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assign new_data_map[33] = new_data[22];
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assign new_data_map[32] = new_data[23];
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assign new_data_map[46] = new_data[24];
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assign new_data_map[47] = new_data[25];
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assign new_data_map[45] = new_data[26];
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assign new_data_map[43] = new_data[27];
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assign new_data_map[40] = new_data[28];
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assign new_data_map[42] = new_data[29];
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assign new_data_map[41] = new_data[30];
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assign new_data_map[44] = new_data[31];
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assign new_data_map[22] = new_data[32];
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assign new_data_map[23] = new_data[33];
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assign new_data_map[21] = new_data[34];
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assign new_data_map[20] = new_data[35];
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assign new_data_map[19] = new_data[36];
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assign new_data_map[18] = new_data[37];
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assign new_data_map[17] = new_data[38];
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assign new_data_map[16] = new_data[39];
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assign new_data_map[30] = new_data[40];
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assign new_data_map[31] = new_data[41];
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assign new_data_map[29] = new_data[42];
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assign new_data_map[27] = new_data[43];
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assign new_data_map[24] = new_data[44];
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assign new_data_map[26] = new_data[45];
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assign new_data_map[25] = new_data[46];
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assign new_data_map[28] = new_data[47];
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assign new_data_map[54] = new_data[48];
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assign new_data_map[55] = new_data[49];
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assign new_data_map[53] = new_data[50];
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assign new_data_map[52] = new_data[51];
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assign new_data_map[50] = new_data[52];
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assign new_data_map[51] = new_data[53];
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assign new_data_map[49] = new_data[54];
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assign new_data_map[48] = new_data[55];
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assign new_data_map[62] = new_data[56];
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assign new_data_map[63] = new_data[57];
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assign new_data_map[61] = new_data[58];
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assign new_data_map[59] = new_data[59];
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assign new_data_map[56] = new_data[60];
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assign new_data_map[58] = new_data[61];
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assign new_data_map[57] = new_data[62];
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assign new_data_map[60] = new_data[63];
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endmodule
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