52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
`timescale 1 ns / 1 ps
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module run_time#
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(
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parameter CLK_PERIOD = 10
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)
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(
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input clk ,
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input rst_n ,
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output reg pulse_ms ,
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output reg [64-1:0] run_time_ms
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam CLKS_OF_MS = 1000000/CLK_PERIOD;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [20-1:0] cnt_clk ;
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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cnt_clk <= 0;
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else if ( cnt_clk == CLKS_OF_MS - 1 )
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cnt_clk <= 0;
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else
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cnt_clk <= cnt_clk + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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pulse_ms <= 1'b0;
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else if ( cnt_clk == CLKS_OF_MS - 1 )
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pulse_ms <= 1'b1;
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else
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pulse_ms <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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run_time_ms <= 0;
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else if ( pulse_ms )
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run_time_ms <= run_time_ms + 1'b1;
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end
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endmodule
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