88 lines
2.0 KiB
Verilog
88 lines
2.0 KiB
Verilog
`timescale 1ns/1ps
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module adg1414_if_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam T_CLK = 10 ; //ns
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localparam DATA_WIDTH = 64 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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wire s_tready ;
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reg [DATA_WIDTH - 1:0] s_tdata ;
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reg s_tvalid ;
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wire sync ;
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wire sclk ;
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wire sdin ;
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reg tx_data ;
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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while (1) begin
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#3_000
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@ ( posedge clk );
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s_tdata <= s_tdata + 1'b1;
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s_tvalid <= 1'b1;
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wait ( s_tready );
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@ ( posedge clk );
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s_tvalid <= 1'b0;
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@ ( posedge clk );
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end
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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s_tvalid <= 1'b0 ;
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s_tdata <= {DATA_WIDTH{1'b1}} ;
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s_tdata[0] <= 1'b0 ;
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end
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endtask
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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adg1414_if#
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(
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.CLK_PERIOD ( 10 ),
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.CLK_DIV ( 4 ),
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.DATA_WIDTH ( DATA_WIDTH )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.s_tready ( s_tready ),
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.s_tvalid ( s_tvalid ),
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.s_tdata ( s_tdata ),
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.sync ( sync ),
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.sclk ( sclk ),
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.sdin ( sdin )
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);
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endmodule |