154 lines
4.4 KiB
Verilog
154 lines
4.4 KiB
Verilog
`timescale 1ns/1ps
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module trans_distribute_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 20; //ns
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parameter CHIPSET_QTY = 4;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [32-1:0] m_axi_trans_tdata ;
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reg m_axi_trans_tlast ;
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wire m_axi_trans_tready ;
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reg m_axi_trans_tvalid ;
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wire [32*CHIPSET_QTY-1:0] axi_txd_tdata_array ;
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wire [ 1*CHIPSET_QTY-1:0] axi_txd_tlast_array ;
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wire [ 1*CHIPSET_QTY-1:0] axi_txd_tready_array ;
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wire [ 1*CHIPSET_QTY-1:0] axi_txd_tvalid_array ;
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wire [32-1:0] axi_txd_tdata[0:CHIPSET_QTY-1] ;
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wire axi_txd_tlast[0:CHIPSET_QTY-1] ;
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reg axi_txd_tready[0:CHIPSET_QTY-1] ;
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wire axi_txd_tvalid[0:CHIPSET_QTY-1] ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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trans_distribute#
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(
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.CHIPSET_QTY ( CHIPSET_QTY )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.s_axi_rx_tdata ( m_axi_trans_tdata ),
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.s_axi_rx_tlast ( m_axi_trans_tlast ),
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.s_axi_rx_tready ( m_axi_trans_tready ),
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.s_axi_rx_tvalid ( m_axi_trans_tvalid ),
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.m_axi_tx_tdata_array ( axi_txd_tdata_array ),
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.m_axi_tx_tlast_array ( axi_txd_tlast_array ),
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.m_axi_tx_tready_array ( axi_txd_tready_array ),
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.m_axi_tx_tvalid_array ( axi_txd_tvalid_array )
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);
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100
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@ ( posedge clk );
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m_axi_trans_tdata <= 1 ;
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m_axi_trans_tdata[25:22]<= 1 ;
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m_axi_trans_tlast <= 1'b0 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 2 ;
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m_axi_trans_tdata[25:22]<= 1 ;
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m_axi_trans_tlast <= 1'b0 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 3 ;
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m_axi_trans_tdata[25:22]<= 1 ;
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m_axi_trans_tlast <= 1'b0 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 4 ;
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m_axi_trans_tdata[25:22]<= 1 ;
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m_axi_trans_tlast <= 1'b1 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 32'h80000005 ;
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m_axi_trans_tdata[27:24]<= 0 ;
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m_axi_trans_tlast <= 1'b1 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 32'hC0000006 ;
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m_axi_trans_tdata[27:24]<= 2 ;
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m_axi_trans_tlast <= 1'b1 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tdata <= 32'hC0000007 ;
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m_axi_trans_tdata[27:24]<= 3 ;
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m_axi_trans_tlast <= 1'b1 ;
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m_axi_trans_tvalid <= 1'b1 ;
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@ ( posedge clk );
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while (~m_axi_trans_tready) @ ( posedge clk );
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m_axi_trans_tlast <= 1'b0 ;
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m_axi_trans_tvalid <= 1'b0 ;
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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m_axi_trans_tdata <= 0 ;
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m_axi_trans_tlast <= 1'b0 ;
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m_axi_trans_tvalid <= 1'b0 ;
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axi_txd_tready[0] <= 1 ;
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axi_txd_tready[1] <= 1 ;
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axi_txd_tready[2] <= 1 ;
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axi_txd_tready[3] <= 1 ;
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end
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endtask
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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genvar i;
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
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assign axi_txd_tready_array[i] = axi_txd_tready[i];
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
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assign axi_txd_tdata[i] = axi_txd_tdata_array[32*i+31 : 32*i];
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assign axi_txd_tlast[i] = axi_txd_tlast_array[i];
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assign axi_txd_tvalid[i] = axi_txd_tvalid_array[i];
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end
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endgenerate
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endmodule |