Files
BSI-901-fpga-software/c64_pro.runs/dds_stim_16ch_synth_1/gen_run.xml
T
2024-10-28 13:14:49 +08:00

46 lines
1.8 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="dds_stim_16ch_synth_1" LaunchPart="xc7z010clg400-2" LaunchTime="1692264074">
<File Type="PA-TCL" Name="dds_stim_16ch.tcl"/>
<File Type="REPORTS-TCL" Name="dds_stim_16ch_reports.tcl"/>
<File Type="RDS-RDS" Name="dds_stim_16ch.vds"/>
<File Type="RDS-UTIL" Name="dds_stim_16ch_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="dds_stim_16ch_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="dds_stim_16ch.dcp"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_stim_16ch" RelGenDir="$PGENDIR/dds_stim_16ch">
<File Path="$PSRCDIR/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dds_stim_16ch"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_stim_16ch" RelGenDir="$PGENDIR/dds_stim_16ch">
<File Path="$PSRCDIR/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="dds_stim_16ch"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>