217 lines
7.5 KiB
C++
217 lines
7.5 KiB
C++
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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#include "smartconnect.h"
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#include <fstream>
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#include <iostream>
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#include <vector>
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#include <sstream>
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using namespace std;
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using namespace xtlm;
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#define __socket_inst(var, role, idx, i) \
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if (var > i) { \
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idx##_AXI_tlm_aximm_read_socket = new xtlm::xtlm_aximm_##role##_socket(#idx "_AXI_tlm_aximm_read_socket", 32); \
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role##_rd_sockets.push_back(idx##_AXI_tlm_aximm_read_socket); \
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idx##_AXI_tlm_aximm_write_socket = new xtlm::xtlm_aximm_##role##_socket(#idx "_AXI_tlm_aximm_write_socket", 32); \
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role##_wr_sockets.push_back(idx##_AXI_tlm_aximm_write_socket); \
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}
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smartconnect::smartconnect(sc_module_name nm, xsc::common_cpp::properties& properties) :
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aclk("aclk"), aclk1("aclk1"), aclk2("aclk2"), aclk3("aclk3"), aclk4("aclk4"), aclk5("aclk5"),
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aclk6("aclk6"), aclk7("aclk7"), aclk8("aclk8"), aclk9("aclk9"), aclk10("aclk10"), aclk11("aclk11"),
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aclk12("aclk12"), aclk13("alck13"), aclk14("aclk14"), aclk15("aclk15") {
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m_report_handler = new xsc::common_cpp::report_handler("smartconnect");
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// TODO: need the component name of the IP instance
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// TODO: acquire SC config from file handoff (sc_xtlm.rtd file)
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filename = "";
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if (properties.hasParameter("TLM_COMPONENT_NAME")) {
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if (m_report_handler->get_verbosity_level()
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== xsc::common_cpp::VERBOSITY::DEBUG) {
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m_ss.str("");
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m_ss << this->name() << "TLM_COMPONENT_NAME is " << properties.getString("TLM_COMPONENT_NAME")<< "\n";
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XSC_REPORT_INFO_VERB((*m_report_handler), "1", m_ss.str().c_str(),
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DEBUG);
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}
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filename = "sc_xtlm_" + properties.getString("TLM_COMPONENT_NAME") + ".mem";
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}
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ifstream rtd_file(filename);
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if (rtd_file.is_open()) {
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if (m_report_handler->get_verbosity_level()
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== xsc::common_cpp::VERBOSITY::DEBUG) {
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m_ss.str("");
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m_ss << this->name() <<"Opened " << filename << std::endl;
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XSC_REPORT_INFO_VERB((*m_report_handler), "1", m_ss.str().c_str(),
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DEBUG);
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}
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} else {
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m_ss.str("");
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m_ss << this->name()<<" Failed to open "<<std::endl;
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XSC_REPORT_ERROR((*m_report_handler), "1", m_ss.str().c_str());
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}
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// ifstream rtd_file("sc_xtlm.mem");
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// if (rtd_file.is_open()) {
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// cout << "Opened sc_xtlm.mem\n";
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// } else {
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// cerr << "Failed to open sc_xtlm.mem";
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// }
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string line;
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while (getline(rtd_file,line)) {
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stringstream ss(line);
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string param_name;
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string param_value;
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ss >> param_name;
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ss >> param_value;
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if (m_report_handler->get_verbosity_level()
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== xsc::common_cpp::VERBOSITY::DEBUG) {
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m_ss.str("");
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m_ss << this->name() << "Loaded: " << param_name << " :: " << param_value << std::endl;
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XSC_REPORT_INFO_VERB((*m_report_handler), "1", m_ss.str().c_str(),
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DEBUG);
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}
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smartconnect_config[param_name] = param_value;
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properties.addString(param_name, param_value);
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}
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int num_si = stoi(smartconnect_config["NUM_SI"]);
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int num_mi = stoi(smartconnect_config["NUM_MI"]);
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__socket_inst(num_si, target, S00, 0)
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__socket_inst(num_si, target, S01, 1)
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__socket_inst(num_si, target, S02, 2)
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__socket_inst(num_si, target, S03, 3)
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__socket_inst(num_si, target, S04, 4)
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__socket_inst(num_si, target, S05, 5)
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__socket_inst(num_si, target, S06, 6)
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__socket_inst(num_si, target, S07, 7)
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__socket_inst(num_si, target, S08, 8)
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__socket_inst(num_si, target, S09, 9)
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__socket_inst(num_si, target, S10, 10)
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__socket_inst(num_si, target, S11, 11)
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__socket_inst(num_si, target, S12, 12)
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__socket_inst(num_si, target, S13, 13)
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__socket_inst(num_si, target, S14, 14)
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__socket_inst(num_si, target, S15, 15)
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__socket_inst(num_mi, initiator, M00, 0)
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__socket_inst(num_mi, initiator, M01, 1)
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__socket_inst(num_mi, initiator, M02, 2)
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__socket_inst(num_mi, initiator, M03, 3)
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__socket_inst(num_mi, initiator, M04, 4)
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__socket_inst(num_mi, initiator, M05, 5)
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__socket_inst(num_mi, initiator, M06, 6)
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__socket_inst(num_mi, initiator, M07, 7)
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__socket_inst(num_mi, initiator, M08, 8)
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__socket_inst(num_mi, initiator, M09, 9)
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__socket_inst(num_mi, initiator, M10, 10)
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__socket_inst(num_mi, initiator, M11, 11)
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__socket_inst(num_mi, initiator, M12, 12)
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__socket_inst(num_mi, initiator, M13, 13)
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__socket_inst(num_mi, initiator, M14, 14)
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__socket_inst(num_mi, initiator, M15, 15)
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core_model = new smartconnect_xtlm("smartconnect_xtlm", properties, smartconnect_config,m_report_handler);
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for (int i = 0; i < num_si; i++) {
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target_rd_sockets[i]->bind(*(core_model->saxi_rd_socket[i]));
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target_wr_sockets[i]->bind(*(core_model->saxi_wr_socket[i]));
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}
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for (int i = 0; i < num_mi; i++) {
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core_model->maxi_rd_socket[i]->bind(*(initiator_rd_sockets[i]));
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core_model->maxi_wr_socket[i]->bind(*(initiator_wr_sockets[i]));
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}
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//Stub Reset Signal if not connected
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if(properties.getLongLong("HAS_RESET") == 0)
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{
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aresetn.bind(aresetn_signal);
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aresetn_signal.write(1);
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}
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}
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#define __clk_tieoff(i) \
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if (num_clks < i+1) { \
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clk_tieoff = new sc_signal<bool>; \
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aclk##i(*clk_tieoff); \
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}
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void smartconnect::before_end_of_elaboration() {
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int num_clks = stoi(smartconnect_config["NUM_CLKS"]);
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sc_signal<bool>* clk_tieoff;
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__clk_tieoff(1)
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__clk_tieoff(2)
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__clk_tieoff(3)
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__clk_tieoff(4)
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__clk_tieoff(5)
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__clk_tieoff(6)
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__clk_tieoff(7)
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__clk_tieoff(8)
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__clk_tieoff(9)
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__clk_tieoff(10)
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__clk_tieoff(11)
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__clk_tieoff(12)
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__clk_tieoff(13)
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__clk_tieoff(14)
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__clk_tieoff(15)
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}
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