53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module pwm_gen#
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(
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parameter DATA_WIDTH = 10
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)
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(
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input clk ,
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input rst_n ,
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input enable ,
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input [DATA_WIDTH-1:0] period ,
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input [DATA_WIDTH-1:0] duty ,
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output reg pwm
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);
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [DATA_WIDTH-1:0] max ;
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reg [DATA_WIDTH-1:0] cnt ;
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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max <= 0;
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else if ( cnt == 0 )
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max <= period;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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cnt <= 0;
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else if ( ~enable )
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cnt <= 0;
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else if ( cnt != max )
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cnt <= cnt + 1'b1;
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else
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cnt <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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pwm <= 1'b0;
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else if ( cnt == duty )
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pwm <= 1'b0;
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else if ( enable && cnt == 0 )
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pwm <= 1'b1;
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end
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endmodule
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