366 lines
11 KiB
Verilog
366 lines
11 KiB
Verilog
`timescale 1 ns / 1 ps
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module upload_protocol_ql#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CHANNLE_QTY = 64 ,
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parameter PRE_MSG_LEN = 128
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)
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(
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input clk ,
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input rst_n ,
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input enable ,
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output interrupt ,
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input pulse_ms ,
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input [64-1:0] run_time_ms ,
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input [ 8*PRE_MSG_LEN-1:0]pre_message_array ,
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input [ 8-1:0] pre_message_length ,
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input [32-1:0] upload_round_qty_set ,
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input reset_package_id ,
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input [32-1:0] package_overtime_ms ,
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input [32-1:0] s_axis_trigger_tdata ,
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input s_axis_trigger_tvalid ,
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output reg s_axis_trigger_tready ,
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input [ 8-1:0] s_axis_eeg_tdata ,
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input s_axis_eeg_tlast ,
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output reg s_axis_eeg_tready ,
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input s_axis_eeg_tvalid ,
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input [48-1:0] accel_data ,
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input m_axis_record_tfull ,
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output reg [ 8-1:0] m_axis_record_tdata ,
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output reg [ 1-1:0] m_axis_record_tkeep ,
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output reg m_axis_record_tlast ,
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input m_axis_record_tready ,
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output reg m_axis_record_tvalid
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam ST_IDLE = 4'd0 ;
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localparam ST_MSG_HEAD = 4'd1 ;
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localparam ST_WAIT = 4'd2 ;
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localparam ST_READ_TRIGGER = 4'd3 ;
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localparam ST_MSG_TRIGGER = 4'd4 ;
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localparam ST_MSG_RECORD = 4'd5 ;
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localparam ST_MSG_CRC = 4'd6 ;
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localparam ST_ADDITIONAL = 4'd7 ;
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localparam ADDL_NUM = 12 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [ 4-1:0] cstate ;
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reg [ 4-1:0] nstate ;
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reg [32-1:0] overtime_ms ;
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reg [32-1:0] package_id ;
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wire [ 8-1:0] pre_message[0:PRE_MSG_LEN-1];
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reg [32-1:0] trigger_word ;
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wire [ 8-1:0] trigger_byte[0:3] ;
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wire [ 8-1:0] msg_crc[0:1] ;
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reg [32-1:0] upload_round_qty ;
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reg [32-1:0] upload_bytes_cnt ;
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wire [32-1:0] upload_bytes_cnt_add1 ;
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reg [32-1:0] upload_rounds_cnt ;
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reg [32-1:0] upload_record_bytes_cnt ;
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wire [16-1:0] crc16_out ;
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reg [16-1:0] crc16 ;
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wire [ 8-1:0] upload_addl[0:ADDL_NUM-1] ;
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reg [ 8-1:0] byte_cnt ;
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reg upload_break ;
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reg upload_disable ;
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wire [ 4-1:0] debug_sig_sort ;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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// Function
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//*****************************************************************************
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function automatic [15:0] crc16_d8;
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input [15:0] crcIn;
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input [7:0] data;
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begin
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crc16_d8[0] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[8] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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crc16_d8[1] = crcIn[9];
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crc16_d8[2] = crcIn[10];
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crc16_d8[3] = crcIn[11];
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crc16_d8[4] = crcIn[12];
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crc16_d8[5] = crcIn[13];
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crc16_d8[6] = crcIn[0] ^ crcIn[14] ^ data[0];
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crc16_d8[7] = crcIn[0] ^ crcIn[1] ^ crcIn[15] ^ data[0] ^ data[1];
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crc16_d8[8] = crcIn[1] ^ crcIn[2] ^ data[1] ^ data[2];
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crc16_d8[9] = crcIn[2] ^ crcIn[3] ^ data[2] ^ data[3];
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crc16_d8[10] = crcIn[3] ^ crcIn[4] ^ data[3] ^ data[4];
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crc16_d8[11] = crcIn[4] ^ crcIn[5] ^ data[4] ^ data[5];
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crc16_d8[12] = crcIn[5] ^ crcIn[6] ^ data[5] ^ data[6];
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crc16_d8[13] = crcIn[6] ^ crcIn[7] ^ data[6] ^ data[7];
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crc16_d8[14] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6];
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crc16_d8[15] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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end
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endfunction
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//*****************************************************************************
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always@( posedge clk or negedge rst_n ) begin
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if( !rst_n ) cstate <= ST_IDLE;
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else cstate <= nstate;
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end
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always@( * ) begin
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case ( cstate )
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ST_IDLE:
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if ( enable && s_axis_eeg_tvalid )
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nstate <= ST_MSG_HEAD;
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else
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nstate <= ST_IDLE;
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ST_MSG_HEAD:
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if ( byte_cnt == pre_message_length - 1 )
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nstate <= ST_WAIT;
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else
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nstate <= ST_MSG_HEAD;
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ST_WAIT:
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if ( !enable || upload_rounds_cnt == upload_round_qty || overtime_ms == package_overtime_ms || (m_axis_record_tfull && !upload_disable) )
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nstate <= ST_MSG_CRC;
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else if ( s_axis_eeg_tvalid )
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nstate <= ST_READ_TRIGGER;
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else
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nstate <= ST_WAIT;
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ST_READ_TRIGGER:
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nstate <= ST_MSG_TRIGGER;
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ST_MSG_TRIGGER:
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if ( byte_cnt == 4-1 )
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nstate <= ST_MSG_RECORD;
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else
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nstate <= ST_MSG_TRIGGER;
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ST_MSG_RECORD:
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if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
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nstate <= ST_WAIT;
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else
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nstate <= ST_MSG_RECORD;
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ST_MSG_CRC:
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if ( byte_cnt == 2-1 )
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nstate <= ST_ADDITIONAL;
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else
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nstate <= ST_MSG_CRC;
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ST_ADDITIONAL:
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if ( byte_cnt == ADDL_NUM-1 )
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nstate <= upload_break? ST_WAIT:ST_IDLE;
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else
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nstate <= ST_ADDITIONAL;
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default:
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nstate <= ST_IDLE;
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endcase
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_break <= 1'b0;
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else if ( cstate == ST_WAIT && (upload_rounds_cnt != upload_round_qty && overtime_ms != package_overtime_ms) && m_axis_record_tfull && !upload_disable )
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upload_break <= 1'b1;
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else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
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upload_break <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_disable <= 1'b0;
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else if ( cstate == ST_ADDITIONAL && nstate != ST_ADDITIONAL )
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upload_disable <= m_axis_record_tfull;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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package_id <= 0;
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else if ( reset_package_id )
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package_id <= 0;
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else if ( cstate == ST_MSG_CRC && nstate == ST_ADDITIONAL )
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package_id <= package_id + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_round_qty <= 0;
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else if ( cstate == ST_IDLE )
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upload_round_qty <= upload_round_qty_set;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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s_axis_trigger_tready <= 1'b0;
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else if ( nstate == ST_READ_TRIGGER )
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s_axis_trigger_tready <= 1'b1;
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else
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s_axis_trigger_tready <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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trigger_word <= 0;
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else if ( s_axis_trigger_tvalid && s_axis_trigger_tready )
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trigger_word <= s_axis_trigger_tdata;
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else if ( cstate != ST_MSG_TRIGGER )
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trigger_word <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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s_axis_eeg_tready <= 1'b0;
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else if ( cstate == ST_MSG_RECORD || nstate == ST_MSG_RECORD )
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s_axis_eeg_tready <= 1'b1;
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else
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s_axis_eeg_tready <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_rounds_cnt <= 0;
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else if ( cstate == ST_IDLE )
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upload_rounds_cnt <= 0;
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else if ( s_axis_eeg_tready && s_axis_eeg_tvalid && s_axis_eeg_tlast )
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upload_rounds_cnt <= upload_rounds_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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overtime_ms <= 0;
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else if ( s_axis_eeg_tvalid )
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overtime_ms <= 0;
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else if ( pulse_ms )
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overtime_ms <= overtime_ms + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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byte_cnt <= 0;
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else if ( cstate != nstate )
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byte_cnt <= 0;
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else
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byte_cnt <= byte_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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m_axis_record_tdata <= 0;
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m_axis_record_tkeep <= 1'b1;
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m_axis_record_tvalid <= 1'b0;
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end else if ( cstate == ST_MSG_HEAD ) begin
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m_axis_record_tdata <= pre_message[byte_cnt];
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m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
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end else if ( cstate == ST_MSG_TRIGGER ) begin
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m_axis_record_tdata <= trigger_byte[byte_cnt];
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m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
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end else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready ) begin
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m_axis_record_tdata <= s_axis_eeg_tdata;
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m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
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end else if ( cstate == ST_MSG_CRC ) begin
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m_axis_record_tdata <= msg_crc[byte_cnt];
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m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
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end else if ( cstate == ST_ADDITIONAL ) begin
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m_axis_record_tdata <= upload_addl[byte_cnt];
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m_axis_record_tvalid <= upload_disable? 1'b0:1'b1;
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end else
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m_axis_record_tvalid <= 1'b0;
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end
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always @ ( posedge clk ) begin
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if ( cstate == ST_IDLE )
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crc16 <= 16'hFFFF;
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else if ( cstate != ST_MSG_CRC && m_axis_record_tvalid && m_axis_record_tready )
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crc16 <= crc16_out;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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m_axis_record_tlast <= 1'b0;
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end else if ( cstate == ST_ADDITIONAL && (byte_cnt == ADDL_NUM-1) ) begin
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m_axis_record_tlast <= 1'b1;
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end else
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m_axis_record_tlast <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_bytes_cnt <= 0;
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else if ( cstate == ST_IDLE )
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upload_bytes_cnt <= 0;
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else if ( (cstate != ST_ADDITIONAL) && m_axis_record_tvalid && m_axis_record_tready )
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upload_bytes_cnt <= upload_bytes_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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upload_record_bytes_cnt <= 0;
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else if ( cstate == ST_IDLE )
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upload_record_bytes_cnt <= 0;
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else if ( cstate == ST_MSG_RECORD && s_axis_eeg_tvalid && s_axis_eeg_tready )
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upload_record_bytes_cnt <= upload_record_bytes_cnt + 1'b1;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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//pre_message[21:14] is run_time_ms
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//pre_message[26:23] is package_id
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generate
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for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pre_msg
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if ( i > 13 && i < 22 )
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assign pre_message[i] = run_time_ms[8*(i-14)+7 : 8*(i-14)];
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else if ( i > 22 && i < 27 )
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assign pre_message[i] = package_id[8*(i-23)+7 : 8*(i-23)];
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else
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assign pre_message[i] = pre_message_array[8*i+7 : 8*i];
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end
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endgenerate
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assign trigger_byte[0] = trigger_word[ 7: 0];
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assign trigger_byte[1] = trigger_word[15: 8];
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assign trigger_byte[2] = trigger_word[23:16];
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assign trigger_byte[3] = trigger_word[31:24];
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assign crc16_out = crc16_d8(crc16, m_axis_record_tdata);
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assign msg_crc[0] = crc16[15: 8];
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assign msg_crc[1] = crc16[ 7: 0];
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assign upload_bytes_cnt_add1 = upload_bytes_cnt + 1'b1;
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assign upload_addl[ 0] = upload_bytes_cnt_add1[ 7: 0];
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assign upload_addl[ 1] = upload_bytes_cnt_add1[15: 8];
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assign upload_addl[ 2] = upload_bytes_cnt_add1[23:16];
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assign upload_addl[ 3] = upload_bytes_cnt_add1[31:24];
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assign upload_addl[ 4] = upload_rounds_cnt[ 7: 0];
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assign upload_addl[ 5] = upload_rounds_cnt[15: 8];
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assign upload_addl[ 6] = upload_rounds_cnt[23:16];
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assign upload_addl[ 7] = upload_rounds_cnt[31:24];
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assign upload_addl[ 8] = upload_record_bytes_cnt[ 7: 0];
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assign upload_addl[ 9] = upload_record_bytes_cnt[15: 8];
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assign upload_addl[10] = upload_record_bytes_cnt[23:16];
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assign upload_addl[11] = upload_record_bytes_cnt[31:24];
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endmodule
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