349 lines
9.4 KiB
Verilog
349 lines
9.4 KiB
Verilog
`timescale 1ns/1ps
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module trans_arrange_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 20; //ns
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parameter SPI_TRANS_PERIOD = 1500; //ns
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [32-1:0] update_period ;
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reg enable_timer ;
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wire trans_round ;
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wire trans_pulse ;
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reg dds_enable ;
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reg dds_reset_n ;
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reg phase_enable ;
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reg [32-1:0] phase_inc[0:16-1] ;
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reg [32-1:0] phase_off[0:16-1] ;
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wire [24*16-1:0] phase_inc_array ;
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wire [24*16-1:0] phase_off_array ;
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reg [ 32-1:0] cnv_cmd[0:16-1] ;
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wire [16*32-1:0] cnv_cmd_array ;
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reg [ 8-1:0] cnv_cmd_lth ;
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reg [ 8-1:0] cnv_divisor ;
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reg [16* 8-1:0] stim_trim_p_array ;
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reg [16* 8-1:0] stim_trim_n_array ;
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reg enable_record ;
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reg enable_stim ;
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wire [16* 9-1:0] sine_wave_array ;
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reg [32-1:0] m_axi_stim_tdata ;
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reg m_axi_stim_tlast ;
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wire m_axi_stim_tready ;
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reg m_axi_stim_tvalid ;
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wire m_axis_tvalid ;
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wire m_axis_tready ;
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wire [32-1:0] m_axis_tdata ;
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wire m_axis_tlast ;
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wire [32-1:0] s_axi_trans_tdata ;
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wire s_axi_trans_tlast ;
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reg s_axi_trans_tready ;
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wire s_axi_trans_tvalid ;
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integer n;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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axis_data_fifo_w32_d32 u_axis_data_fifo_w32_d32
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(
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.s_axis_aclk ( clk ),
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.s_axis_aresetn ( 1'b1 ),
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.s_axis_tvalid ( m_axi_stim_tvalid ),
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.s_axis_tready ( m_axi_stim_tready ),
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.s_axis_tdata ( m_axi_stim_tdata ),
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.s_axis_tlast ( m_axi_stim_tlast ),
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.m_axis_tvalid ( m_axis_tvalid ),
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.m_axis_tready ( m_axis_tready ),
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.m_axis_tdata ( m_axis_tdata ),
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.m_axis_tlast ( m_axis_tlast )
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);
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trans_timer#
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(
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.CLK_PERIOD ( T_CLK ),
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.SPI_TRANS_PERIOD ( SPI_TRANS_PERIOD )
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)
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u_trans_timer
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( enable_timer ),
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.update_period ( update_period ),
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.update ( trans_round ),
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.trans ( trans_pulse )
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);
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sine_gen u_sine_wave_gen
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.aclken ( dds_enable ),
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.aresetn ( dds_reset_n ),
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.phase_enable ( phase_enable ),
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.phase_inc_array ( phase_inc_array ),
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.phase_off_array ( phase_off_array ),
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.update ( trans_round ),
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.sine_wave_array ( sine_wave_array )
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);
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trans_arrange#
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(
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.REG_ADDR_MONITOR ( 8'd40 ),
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.REG_ADDR_STIM_POL ( 8'd44 ),
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.REG_ADDR_POS_CUR ( 8'd64 ),
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.REG_ADDR_NEG_CUR ( 8'd96 )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.cnv_cmd_array ( cnv_cmd_array ),
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.cnv_cmd_lth ( cnv_cmd_lth ),
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.cnv_divisor ( cnv_divisor ), //<8>
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.stim_trim_p ( stim_trim_p_array ), //<8*16>
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.stim_trim_n ( stim_trim_n_array ), //<8*16>
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.enable_record ( enable_record ),
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.enable_stim ( enable_stim ),
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.trans_round ( trans_round ),
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//--------------------------------------------------From DDS
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.sine_wave_array ( sine_wave_array ), //<9*16>
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//--------------------------------------------------From PS
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.s_axi_stim_tdata ( m_axis_tdata ),
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.s_axi_stim_tlast ( m_axis_tlast ),
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.s_axi_stim_tready ( m_axis_tready ),
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.s_axi_stim_tvalid ( m_axis_tvalid ),
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//--------------------------------------------------To trans_distribute
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.m_axi_trans_tdata ( s_axi_trans_tdata ),
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.m_axi_trans_tlast ( s_axi_trans_tlast ),
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.m_axi_trans_tready ( s_axi_trans_tready ),
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.m_axi_trans_tvalid ( s_axi_trans_tvalid )
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);
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100
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@ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b00; //need fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 5; //stim ch
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m_axi_stim_tdata[15: 9] <= 0; //sine ch
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m_axi_stim_tdata[ 8: 0] <= 9'h000; //gain_c
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m_axi_stim_tvalid <= 1'b1;
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m_axi_stim_tlast <= 1'b0;
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b00; //need fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 6; //stim ch
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m_axi_stim_tdata[15: 9] <= 1; //sine ch
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m_axi_stim_tdata[ 8: 0] <= 9'h100; //gain_c
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b10; //un fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 64+7; //write reg
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m_axi_stim_tdata[15: 8] <= 0; //trim
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m_axi_stim_tdata[ 7: 0] <= 8'h78; //magnitude
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b10; //un fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 44; //write reg
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m_axi_stim_tdata[15: 0] <= 16'h0001<<7; //polarity
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m_axi_stim_tlast <= 1'b1;
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tvalid <= 1'b0;
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m_axi_stim_tlast <= 1'b0;
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#100
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@ ( posedge clk );
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dds_enable <= 1'b1;
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dds_reset_n <= 1'b1;
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enable_record <= 1'b1;
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enable_stim <= 1'b1;
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enable_timer <= 1'b1;
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for(n=1;n<10;n=n+1) begin
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#100
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@ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b00; //need fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 5; //stim ch
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m_axi_stim_tdata[15: 9] <= 0; //sine ch
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m_axi_stim_tdata[ 8: 0] <= 9'h000; //gain_c
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m_axi_stim_tvalid <= 1'b1;
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m_axi_stim_tlast <= 1'b0;
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b00; //need fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 6; //stim ch
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m_axi_stim_tdata[15: 9] <= 1; //sine ch
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m_axi_stim_tdata[ 8: 0] <= 9'h100; //gain_c
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b10; //un fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 64+7; //write reg
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m_axi_stim_tdata[15: 8] <= 0; //trim
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m_axi_stim_tdata[ 7: 0] <= 8'h79; //magnitude
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tdata[31:30] <= 2'b10; //un fill
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m_axi_stim_tdata[29:24] <= 0;
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m_axi_stim_tdata[23:16] <= 44; //write reg
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m_axi_stim_tdata[15: 0] <= 16'h0001<<7; //polarity
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m_axi_stim_tlast <= 1'b1;
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@ ( posedge clk );
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while (~m_axi_stim_tready) @ ( posedge clk );
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m_axi_stim_tvalid <= 1'b0;
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m_axi_stim_tlast <= 1'b0;
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end
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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update_period <= (SPI_TRANS_PERIOD*7)/T_CLK;
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cnv_cmd_lth <= 3;
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cnv_cmd[ 0] <= 32'h00010000;
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cnv_cmd[ 1] <= 32'h00020000;
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cnv_cmd[ 2] <= 32'h00030000;
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cnv_cmd[ 3] <= 32'h00000000;
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cnv_cmd[ 4] <= 32'h00000000;
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cnv_cmd[ 5] <= 32'h00000000;
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cnv_cmd[ 6] <= 32'h00000000;
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cnv_cmd[ 7] <= 32'h00000000;
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cnv_cmd[ 8] <= 32'h00000000;
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cnv_cmd[ 9] <= 32'h00000000;
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cnv_cmd[10] <= 32'h00000000;
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cnv_cmd[11] <= 32'h00000000;
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cnv_cmd[12] <= 32'h00000000;
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cnv_cmd[13] <= 32'h00000000;
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cnv_cmd[14] <= 32'h00000000;
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cnv_cmd[15] <= 32'h00000000;
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cnv_divisor <= 0;
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stim_trim_p_array <= 0;
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stim_trim_n_array <= 0;
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phase_enable <= 1'b0;
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phase_inc[ 0] <= 0;
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phase_inc[ 1] <= 0;
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phase_inc[ 2] <= 0;
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phase_inc[ 3] <= 0;
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phase_inc[ 4] <= 0;
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phase_inc[ 5] <= 0;
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phase_inc[ 6] <= 0;
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phase_inc[ 7] <= 0;
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phase_inc[ 8] <= 0;
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phase_inc[ 9] <= 0;
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phase_inc[10] <= 0;
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phase_inc[11] <= 0;
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phase_inc[12] <= 0;
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phase_inc[13] <= 0;
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phase_inc[14] <= 0;
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phase_inc[15] <= 0;
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phase_off[ 0] <= 0;
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phase_off[ 1] <= 0;
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phase_off[ 2] <= 0;
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phase_off[ 3] <= 0;
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phase_off[ 4] <= 0;
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phase_off[ 5] <= 0;
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phase_off[ 6] <= 0;
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phase_off[ 7] <= 0;
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phase_off[ 8] <= 0;
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phase_off[ 9] <= 0;
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phase_off[10] <= 0;
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phase_off[11] <= 0;
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phase_off[12] <= 0;
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phase_off[13] <= 0;
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phase_off[14] <= 0;
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phase_off[15] <= 0;
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dds_enable <= 1'b0;
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dds_reset_n <= 1'b0;
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enable_record <= 1'b0;
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enable_stim <= 1'b0;
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enable_timer <= 1'b0;
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s_axi_trans_tready <= 1'b1;
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m_axi_stim_tdata <= 0;
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m_axi_stim_tlast <= 1'b0;
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m_axi_stim_tvalid <= 1'b0;
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end
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endtask
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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genvar i;
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generate
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for(i=0;i<16;i=i+1) begin : pack
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assign phase_inc_array[24*i+23 : 24*i] = phase_inc[i];
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assign phase_off_array[24*i+23 : 24*i] = phase_off[i];
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assign cnv_cmd_array[32*i+31 : 32*i] = cnv_cmd[i];
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end
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endgenerate
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endmodule |