156 lines
5.5 KiB
Verilog
156 lines
5.5 KiB
Verilog
`timescale 1 ns / 1 ps
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module stim_monitor#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CHECK_PERIOD_MS = 1000 // <=1000
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)
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(
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input clk ,
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input rst_n ,
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input [64-1:0] stim_monitor_in ,
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output [64-1:0] stim_monitor_rt ,
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output reg [64-1:0] stim_monitor_latch
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam CLKS_OF_MS = 1000*1000/CLK_PERIOD;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [20-1:0] clk_cnt ;
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reg pulse_ms ;
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reg [12-1:0] latch_period ;
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wire [64-1:0] monitor_in_map ;
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reg [64-1:0] monitor_latch ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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clk_cnt <= 0;
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else if ( clk_cnt == CLKS_OF_MS - 1 )
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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pulse_ms <= 1'b0;
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else if ( clk_cnt == CLKS_OF_MS - 1 )
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pulse_ms <= 1'b1;
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else
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pulse_ms <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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latch_period <= 0;
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else if ( pulse_ms ) begin
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if ( latch_period == CHECK_PERIOD_MS - 1 )
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latch_period <= 0;
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else
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latch_period <= latch_period + 1'b1;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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monitor_latch <= 0;
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else if ( pulse_ms && (latch_period == CHECK_PERIOD_MS - 1) )
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monitor_latch <= 0;
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else
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monitor_latch = monitor_latch | monitor_in_map;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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stim_monitor_latch <= 0;
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else if ( pulse_ms && (latch_period == CHECK_PERIOD_MS - 1) )
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stim_monitor_latch <= monitor_latch;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign monitor_in_map[ 0] = stim_monitor_in[55];
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assign monitor_in_map[ 1] = stim_monitor_in[56];
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assign monitor_in_map[ 2] = stim_monitor_in[54];
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assign monitor_in_map[ 3] = stim_monitor_in[57];
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assign monitor_in_map[ 4] = stim_monitor_in[34];
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assign monitor_in_map[ 5] = stim_monitor_in[35];
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assign monitor_in_map[ 6] = stim_monitor_in[32];
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assign monitor_in_map[ 7] = stim_monitor_in[52];
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assign monitor_in_map[ 8] = stim_monitor_in[38];
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assign monitor_in_map[ 9] = stim_monitor_in[10];
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assign monitor_in_map[10] = stim_monitor_in[11];
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assign monitor_in_map[11] = stim_monitor_in[58];
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assign monitor_in_map[12] = stim_monitor_in[59];
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assign monitor_in_map[13] = stim_monitor_in[ 9];
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assign monitor_in_map[14] = stim_monitor_in[15];
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assign monitor_in_map[15] = stim_monitor_in[13];
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assign monitor_in_map[16] = stim_monitor_in[30];
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assign monitor_in_map[17] = stim_monitor_in[19];
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assign monitor_in_map[18] = stim_monitor_in[48];
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assign monitor_in_map[19] = stim_monitor_in[61];
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assign monitor_in_map[20] = stim_monitor_in[49];
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assign monitor_in_map[21] = stim_monitor_in[37];
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assign monitor_in_map[22] = stim_monitor_in[60];
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assign monitor_in_map[23] = stim_monitor_in[ 8];
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assign monitor_in_map[24] = stim_monitor_in[36];
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assign monitor_in_map[25] = stim_monitor_in[53];
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assign monitor_in_map[26] = stim_monitor_in[33];
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assign monitor_in_map[27] = stim_monitor_in[63];
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assign monitor_in_map[28] = stim_monitor_in[51];
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assign monitor_in_map[29] = stim_monitor_in[62];
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assign monitor_in_map[30] = stim_monitor_in[39];
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assign monitor_in_map[31] = stim_monitor_in[50];
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assign monitor_in_map[32] = stim_monitor_in[28];
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assign monitor_in_map[33] = stim_monitor_in[18];
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assign monitor_in_map[34] = stim_monitor_in[29];
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assign monitor_in_map[35] = stim_monitor_in[27];
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assign monitor_in_map[36] = stim_monitor_in[17];
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assign monitor_in_map[37] = stim_monitor_in[31];
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assign monitor_in_map[38] = stim_monitor_in[26];
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assign monitor_in_map[39] = stim_monitor_in[16];
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assign monitor_in_map[40] = stim_monitor_in[24];
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assign monitor_in_map[41] = stim_monitor_in[25];
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assign monitor_in_map[42] = stim_monitor_in[22];
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assign monitor_in_map[43] = stim_monitor_in[46];
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assign monitor_in_map[44] = stim_monitor_in[44];
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assign monitor_in_map[45] = stim_monitor_in[23];
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assign monitor_in_map[46] = stim_monitor_in[20];
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assign monitor_in_map[47] = stim_monitor_in[21];
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assign monitor_in_map[48] = stim_monitor_in[ 6];
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assign monitor_in_map[49] = stim_monitor_in[ 3];
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assign monitor_in_map[50] = stim_monitor_in[ 4];
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assign monitor_in_map[51] = stim_monitor_in[43];
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assign monitor_in_map[52] = stim_monitor_in[ 2];
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assign monitor_in_map[53] = stim_monitor_in[42];
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assign monitor_in_map[54] = stim_monitor_in[14];
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assign monitor_in_map[55] = stim_monitor_in[40];
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assign monitor_in_map[56] = stim_monitor_in[12];
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assign monitor_in_map[57] = stim_monitor_in[41];
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assign monitor_in_map[58] = stim_monitor_in[ 0];
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assign monitor_in_map[59] = stim_monitor_in[ 1];
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assign monitor_in_map[60] = stim_monitor_in[47];
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assign monitor_in_map[61] = stim_monitor_in[45];
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assign monitor_in_map[62] = stim_monitor_in[ 7];
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assign monitor_in_map[63] = stim_monitor_in[ 5];
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assign stim_monitor_rt = monitor_in_map;
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endmodule
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