116 lines
2.5 KiB
Verilog
116 lines
2.5 KiB
Verilog
`timescale 1ns/1ps
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module ads1299_spi_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 20; //ns
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg trans ;
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wire rdy ;
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reg start ;
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reg [32 - 1:0] din ;
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wire done ;
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wire [32 - 1:0] dout ;
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wire cs ;
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wire sclk ;
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wire mosi ;
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wire miso ;
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reg [32 - 1:0] data ;
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reg [ 8 - 1:0] cnt ;
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//GSR GSR(.GSRI(1'b1));
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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trans <= 1'b0 ;
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else if (cs) begin
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#200 trans <= 1'b1;
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#20 trans <= 1'b0;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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start <= 1'b0;
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din <= 0;
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data <= 0;
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end else if ( trans ) begin
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start <= 1'b1;
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din <= 32'hAAAA5555;//$random;
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data <= 32'hCCCCAAA5;//$random;
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end else
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start <= 1'b0;
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end
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always @ ( negedge sclk or negedge rst_n or posedge cs ) begin
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if( !rst_n )
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cnt <= 8'd31;
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else if( cs )
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cnt <= 8'd31;
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else if ( cnt != 0 )
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cnt <= cnt - 1'b1;
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end
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assign miso = data[cnt];
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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end
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endtask
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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ads1299_spi#
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(
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.CLK_PERIOD ( 50 ),
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.CLK_DIV ( 2 ),
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.DATA_WIDTH ( 32 )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.rdy ( rdy ),
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.start ( start ),
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.din ( din ),
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.done ( done ),
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.dout ( dout ),
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.cs ( cs ),
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.sclk ( sclk ),
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.mosi ( mosi ),
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.miso ( miso )
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);
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endmodule |