1986 lines
1.2 MiB
Plaintext
1986 lines
1.2 MiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Fri Sep 4 15:37:38 2026
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| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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| Command : report_control_sets -verbose -file c64pro_top_control_sets_placed.rpt
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| Design : c64pro_top
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| Device : xc7z020
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Control Set Information
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Table of Contents
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-----------------
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1. Summary
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2. Histogram
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3. Flip-Flop Distribution
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4. Detailed Control Set Information
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1. Summary
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----------
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+----------------------------------------------------------+-------+
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| Status | Count |
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+----------------------------------------------------------+-------+
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| Total control sets | 1907 |
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| Minimum number of control sets | 1907 |
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| Addition due to synthesis replication | 0 |
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| Addition due to physical synthesis replication | 0 |
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| Unused register locations in slices containing registers | 5270 |
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+----------------------------------------------------------+-------+
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* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
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** Run report_qor_suggestions for automated merging and remapping suggestions
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2. Histogram
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------------
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+--------------------+-------+
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| Fanout | Count |
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+--------------------+-------+
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| Total control sets | 1907 |
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| >= 0 to < 4 | 476 |
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| >= 4 to < 6 | 190 |
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| >= 6 to < 8 | 72 |
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| >= 8 to < 10 | 297 |
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| >= 10 to < 12 | 37 |
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| >= 12 to < 14 | 73 |
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| >= 14 to < 16 | 14 |
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| >= 16 | 748 |
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+--------------------+-------+
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* Control sets can be remapped at either synth_design or opt_design
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3. Flip-Flop Distribution
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-------------------------
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| No | No | No | 6791 | 1762 |
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| No | No | Yes | 1360 | 488 |
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| No | Yes | No | 3430 | 1314 |
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| Yes | No | No | 4666 | 1228 |
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| Yes | No | Yes | 11217 | 4358 |
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| Yes | Yes | No | 6330 | 1659 |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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4. Detailed Control Set Information
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-----------------------------------
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/sclk_r_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_r_node_1/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_r_node_3/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/sig_addr_posted_cntr_reg[3]_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_w_node_3/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_token_cntr[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[28]_i_1_n_0 | | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/sig_posted_to_axi_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/sclk_r_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_start_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_b_node_3/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_ar_node_3/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_ar_node_4/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_aw_node_4/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/sig_posted_to_axi_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_aw_node_3/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_w_node_7/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_b_node_7/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_r_node_7/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_aw_node_7/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_ar_node_7/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_w_node_6/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_r_node_6/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_b_node_6/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_aw_node_6/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_ar_node_6/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_w_node_5/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_r_node_5/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_b_node_5/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.gen_rthread_loop[0].r_split_fifo/gen_srls[0].srl_nx1/shift_qual | | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_aw_node_5/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_ar_node_5/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_w_node_4/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_r_node_4/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_b_node_4/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.gen_wthread_loop[0].b_split_fifo/gen_srls[0].srl_nx1/shift_qual | | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_b_node_1/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_aw_node_1/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_ar_node_1/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_w_node_0/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_r_node_0/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_aw_node_0/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_ar_node_0/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_b_node_0/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_w_node_2/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_r_node_2/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_b_node_2/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_ar_node_2/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_aw_node_2/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_w_node_1/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/sig_sm_ld_dre_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 2 | 2.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 1 | 2 | 2.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_m_valid_out_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr[9]_i_1_n_0 | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr[9]_i_1_n_0 | 1 | 2 | 2.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/id_state[1]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce_int[0] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_start_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[2] | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr[9]_i_1_n_0 | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce_int[0] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce_int[0] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/SR[0] | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 2 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 2 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1088]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1088]_i_1_n_0 | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[3].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[2].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_iport0_o[0] | 1 | 3 | 3.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/AS[0] | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 3 | 3.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/AS[0] | 1 | 3 | 3.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 1 | 3 | 3.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp | | 1 | 3 | 3.00 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld_temp_1_reg_n_0 | | 3 | 3 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/AS[0] | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2]_i_1__0_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_wr_rst_ic_reg_0 | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[2]_i_1_n_0 | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/AS[0] | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_wr_rst_ic_reg_0 | 2 | 3 | 1.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/m_vector_i | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/gen_srls[3].srl_nx1/shift | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/skid_buffer[1090]_i_1__1_n_0 | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_exit_pipeline/m02_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_exit_pipeline/m01_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_exit_pipeline/m03_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_b_node_0/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_exit_pipeline/m04_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_exit_pipeline/m05_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_exit_pipeline/m06_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_exit_pipeline/m07_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_exit_pipeline/m08_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_exit_pipeline/m09_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_ar_node_4/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_aw_node_4/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_r_node_3/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_w_node_3/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_pipelined.mesg_reg | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_b_node_3/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_ar_node_3/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_aw_node_3/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_w_node_2/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_r_node_2/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_srls[17].srl_nx1/shift_qual | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_b_node_2/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_ar_node_2/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_aw_node_2/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_w_node_1/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_r_node_1/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_exit_pipeline/m10_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m10_nodes/m10_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_exit_pipeline/m11_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m11_nodes/m11_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_exit_pipeline/m12_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m12_nodes/m12_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_exit_pipeline/m13_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m13_nodes/m13_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_exit_pipeline/m14_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m14_nodes/m14_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_exit_pipeline/m15_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m15_nodes/m15_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_exit_pipeline/m16_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m16_nodes/m16_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_exit_pipeline/m17_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m17_nodes/m17_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_exit_pipeline/m18_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m18_nodes/m18_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_exit_pipeline/m19_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m19_nodes/m19_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_exit_pipeline/m20_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m20_nodes/m20_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_exit_pipeline/m21_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m21_nodes/m21_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_srls[3].srl_nx1/shift_qual | | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_ar_node_0/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_aw_node_0/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_r_node_0/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_w_node_0/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_ar_node_1/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_aw_node_1/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_b_node_1/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_b_node_4/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_r_node_4/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_w_node_4/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_ar_node_5/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_aw_node_5/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_b_node_5/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_r_node_5/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_w_node_5/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_ar_node_6/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_aw_node_6/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_b_node_6/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_r_node_6/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_w_node_6/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_ar_node_7/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_aw_node_7/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_r_node_7/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_b_node_7/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_w_node_7/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[46].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[61].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[25].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdyCount[5]_i_2_n_0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdyCount[5]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 | | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_si_converter/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[45].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2[19]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[49].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[24].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[23].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.gen_wthread_loop[0].b_split_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[21].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[52].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.gen_rthread_loop[0].r_split_fifo/fifoaddr[3]_i_1__1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg[0] | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[59].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[58].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[57].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[60].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[43].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[36].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[35].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[51].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[34].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[50].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[37].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[56].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_1[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_si_converter/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[55].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[54].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/fifoaddr[3]_i_1__3_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[53].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/fifoaddr[3]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[28].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[27].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/areset | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/s_den_o_INST_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/wr_control_reg | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_iport0_o[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/areset_r_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[26].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[29].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[44].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[42].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[41].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/EXT_LPF/lpf_int | 2 | 4 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[68].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[67].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_stim_config/eeg_emg_sel[1]_i_2_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2[19]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld_temp_1 | | 4 | 4 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld_temp_1_reg_n_0 | | 4 | 4 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/fifoaddr[3]_i_1__2_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/areset_r_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[66].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[65].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[48].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[47].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[62].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[63].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[64].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[18].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[20].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[32].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[30].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[31].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[40].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[38].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[39].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[14].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[15].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/s_axi_lite_awaddr[6] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[13].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[69].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[70].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_srl_fff/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 | | 1 | 4 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp | | 1 | 4 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp | | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SS[0] | 1 | 4 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]_0[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg[0] | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_coelsc_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_coelsc_cmd_cmplt_reg_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/SR[0] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 | | 2 | 4 | 2.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/SYNC_reg | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/gen_endpoint.w_push_done_reg[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset_d | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset_d | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[7].srl_nx1/shift | | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/gen_endpoint.w_push_done_reg[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/areset_d | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/areset_d | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 5 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[7].srl_nx1/shift | | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/gen_endpoint.w_push_done_reg[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/areset_d | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/curr_read_block0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/curr_read_block[4]_i_1_n_0 | 3 | 5 | 1.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdy_ffa | u_ila_0/inst/ila_core_inst/u_ila_regs/shift_reg10 | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdy_ff9 | u_ila_0/inst/ila_core_inst/u_ila_regs/shift_reg00 | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/gen_pipelined.mesg_reg | | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/areset_d | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/gen_srls[4].srl_nx1/shift_qual | | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 1 | 5 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[7].srl_nx1/shift | | 2 | 5 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 2 | 5 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_ad7689_dual_ctrl/cnv_start | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[1144]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[146]_i_1_n_0 | 3 | 6 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_4 | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_ad7689_dual_ctrl/cnv_start | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_config/eeg_cr_r[31]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[6]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/m_axi_mm2s_rlast_0 | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/areset_r_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/SR[0] | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[1144]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[146]_i_1__0_n_0 | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[6]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 6 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/reset_out[5]_i_1_n_0 | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/areset_r_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_4 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/areset_r_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/PROBE_IN_INST/Read_int | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/PROBE_IN_INST/addr_count_reg0 | 2 | 6 | 3.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SEL | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/GPIO/U0/gpio_core_1/Read_Reg_Rst | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[6]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 5 | 7 | 1.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/m_sc_areset_r | 5 | 7 | 1.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/cmnds_queued_reg_0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/xsdb_rden_ffa | u_ila_0/inst/ila_core_inst/u_ila_regs/count10 | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/xsdb_rden_ff9 | u_ila_0/inst/ila_core_inst/u_ila_regs/count00 | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/s_do_o[0] | 3 | 7 | 2.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_burst_dbeat_cntr_reg[6][0] | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/s2mm_all_idle | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1][0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/clear | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/mm2s_all_idle | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_burst_dbeat_cntr_reg[6][0] | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/cmnds_queued_reg_0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_tvalid_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/counter[7]_i_1_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/r_tvalid_reg[0] | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/p_4_in | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/read_flag | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_SYNC/iSYNC_WORD[6]_i_1_n_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/r_tlast_reg_1 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/trans_cnt_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/ch[7]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/ch[7]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_upload/scan_cnt | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/read_flag | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/trans_cnt | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/r_cnt | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/t_tvalid_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[1][7]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/t_cnt[7]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[2][7]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[0][7]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/gpio_core_1/Read_Reg_Rst | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/read_flag | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/E[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/trans_cnt | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/ch[7]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/m_axis_eegY_tvalid | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 8 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[0][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[12][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[44][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_cur_monitor/scan_cnt[7]_i_1_n_0 | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[32][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[4][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[52][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[56][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[48][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[16][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[20][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[40][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[36][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[28][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[24][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[60][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[8][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[100][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[112][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[12][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[16][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 8 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[20][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/gpio_core_1/Read_Reg_Rst | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[24][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[28][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[108][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[116][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[124][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[120][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[0][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[104][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[44][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[32][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[48][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[40][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[36][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[56][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[52][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[4][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[60][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[68][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[64][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[72][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[76][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[80][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[84][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[88][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[8][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[92][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[96][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message_length[7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/upload_ch[4][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/upload_ch[0][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/m_axis_record_tvalid_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/m_axis_record_tdata[7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/m_axis_eegY_tvalid | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 8 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPIXfer_done_int_pulse_d1 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_01100 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_00110 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/SPICR_data_int_reg0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/SPICR_data_int_reg0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_b_node_6/inst/inst_si_handler/areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_r_node_6/inst/inst_si_handler/areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_r_node_7/inst/inst_si_handler/areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_b_node_7/inst/inst_si_handler/areset_r | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SS[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 3 | 8 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_m_valid_out_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_clr_dbc_reg_reg[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/SS[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_clr_dbc_reg_reg_0[0] | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst | 3 | 8 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/s_axi_lite_wdata[16][0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_m_valid_out_reg_1[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_clr_dbc_reg_reg_0[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_m_valid_out_reg_1[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPIXfer_done_int_pulse_d1 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_00110 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_01100 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/s_axi_lite_wdata[16][0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg[0] | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 4 | 8 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_aw_node_2/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/s_axi_lite_wdata[16][0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/m_axi_rready | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/grant_i[7]_i_1_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/r_beats[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/m_axi_bready_i_reg_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/grant_i[7]_i_1_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/last_grant | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_si_handler/areset_r_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/last_grant | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_si_handler/areset_r_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPIXfer_done_int_pulse_d1 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_01100 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/rx_shft_reg_mode_00110 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/r_cnt | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[1][7]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[2][7]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[0][7]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_cnt[7]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_tvalid_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_0[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_3[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_ad7689_dual_ctrl/dead_cnt[7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_ad7689_dual_ctrl/clk_cnt[31]_i_2_n_0 | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/trans_cnt | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/trans_cnt | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/m_axis_record_tvalid_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/upload_ch[0][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/upload_ch[4][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[12][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[20][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[0][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[24][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[28][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[36][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[16][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[32][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[44][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[40][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[48][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[4][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[52][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[56][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[60][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[8][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[12][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[104][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[112][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[20][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[0][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[116][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[100][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[120][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[124][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[16][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[108][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[44][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[28][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[36][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[32][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[24][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[40][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[48][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[56][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[52][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[4][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[68][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[64][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[60][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[76][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[72][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[80][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[88][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[92][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 8 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message_length[7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[96][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 8 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[84][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[8][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/SPICR_data_int_reg0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/m_axis_record_tdata[7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[9][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 7 | 8 | 1.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[12][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[0][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[13][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[10][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[2][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[5][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[7][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[1][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[11][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[8][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[14][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[4][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[3][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/ch_map[6][7]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_upload/scan_cnt | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[0][7]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[1][7]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/r_cnt | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[2][7]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_cnt[7]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 2 | 9 | 4.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/b_cnt[8]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/b_cnt[8]_i_1_n_0 | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_01 | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/eeg_cr_r[31]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg[1][8]_i_1_n_0 | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1_n_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/ar_cnt[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 9 | 1.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_eop_halt_xfer_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[3].sig_output_data_reg[3][8]_i_1_n_0 | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_aw_node_4/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 5 | 9 | 1.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_eop_halt_xfer_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[2].sig_output_data_reg[2][8]_i_1_n_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 4 | 9 | 2.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/sel | u_ila_0/inst/ila_core_inst/u_ila_regs/clk_lost_cnt[7]_i_1_n_0 | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_eop_halt_xfer_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[2].sig_output_data_reg[2][8]_i_1_n_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_eop_halt_xfer_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[3].sig_output_data_reg[3][8]_i_1_n_0 | 2 | 9 | 4.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_valid_fifo_ld12_out | | 3 | 9 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1_n_0 | 3 | 9 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg[1][8]_i_1_n_0 | 3 | 9 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_valid_fifo_ld12_out | | 3 | 9 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 9 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 9 | 2.25 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_211_in | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/w_cnt[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 2 | 9 | 4.50 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 10 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 10 | 2.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[1]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg_reg[1]0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_1_n_0 | 2 | 10 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg[2][9]_i_1_n_0 | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/O | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg[2][9]_i_1_n_0 | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[3]_1[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg_reg[0]0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg[0][9]_i_1_n_0 | 4 | 10 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 10 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg_reg[1]0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_1_n_0 | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[1]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0[0] | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[2]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg_reg[0]0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg[0][9]_i_1_n_0 | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[0]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1[0] | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/SR[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 10 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[3]_1[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[2]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[0]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/E[0] | | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/read_addr0 | | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/O | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 2 | 11 | 5.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_acq_collect/FSM_sequential_cstate_i_2_n_0 | 5 | 11 | 2.20 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 3 | 11 | 3.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 11 | 2.75 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 3 | 11 | 3.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 11 | 2.75 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/wroute_vacancy | | 3 | 11 | 3.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 12 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_b_node_4/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_r_node_3/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_r_node_2/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_b_node_2/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_r_node_1/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_b_node_0/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_r_node_0/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_b_node_1/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_r_node_4/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_b_node_5/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_r_node_5/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_b_node_3/inst/inst_si_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 3 | 12 | 4.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[19]_i_1_n_0 | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[19]_i_1_n_0 | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/s_sc_handshake[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 12 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 5 | 12 | 2.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 2 | 12 | 6.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[1] | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 3 | 12 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/gen_endpoint.gen_r_singleorder.r_singleorder/gen_id_reg.s_rid_i0 | | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[19]_i_1_n_0 | 3 | 12 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/ar_addr_d[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/aw_addr[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_id_reg.s_rid_i0 | | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[1] | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.s_axi_rid_i | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 5 | 12 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_ar_node_4/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 5 | 13 | 2.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 5 | 13 | 2.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 2 | 13 | 6.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 5 | 13 | 2.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_aw_node_7/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[148]_i_1_n_0 | | 4 | 13 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_ar_node_6/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[148]_i_1_n_0 | | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_aw_node_6/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[148]_i_1_n_0 | | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_ar_node_7/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[148]_i_1_n_0 | | 4 | 13 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 13 | 4.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 2 | 13 | 6.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_ar_node_2/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 2 | 13 | 6.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 3 | 13 | 4.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 5 | 13 | 2.60 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 3 | 13 | 4.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 3 | 13 | 4.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u0_fifo_generator_1_i_1_n_0 | 5 | 13 | 2.60 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_ar_node_0/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 7 | 14 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_aw_node_0/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_ar_node_1/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 3 | 14 | 4.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_aw_node_1/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_ar_node_3/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 5 | 14 | 2.80 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_aw_node_5/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 3 | 14 | 4.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_aw_node_3/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_ar_node_5/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 5 | 14 | 2.80 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg_ns | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 5 | 15 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/areset_r_0 | 6 | 15 | 2.50 |
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|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[1] | 3 | 16 | 5.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[0][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 4 | 16 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/crc16[15]_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/upload_round_qty | 5 | 16 | 3.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/ch | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/U_XSDB_SLAVE/reg_test0 | | 5 | 16 | 3.20 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/wr_probe_out_modified | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/clear_int | 5 | 16 | 3.20 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 2 | 16 | 8.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0][0] | | 2 | 16 | 8.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_reg[6][0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 3 | 16 | 5.33 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[12][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 3 | 16 | 5.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[1][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[3][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[4][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[14][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/crc160 | u_pl_top/u1_upload_top/u_upload_protocol_intan/upload_round_qty_1 | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/sck_neg | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[13][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/sck_neg | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[8][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 11 | 16 | 1.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[9][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[14][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 11 | 16 | 1.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[13][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 10 | 16 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[5][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[1] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/ch | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/xsdb_addr_8_p2 | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[1][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[7][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[3][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[6][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 12 | 16 | 1.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[2][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 10 | 16 | 1.60 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[10][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 10 | 16 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[4][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 10 | 16 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[11][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 10 | 16 | 1.60 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[12][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_ch_map/current[15][15]_i_2_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/E[0] | | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_81/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_82/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_84/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/areset_r_0 | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_18/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_19/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 8 | 16 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_6/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_3[15]_i_1_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_80/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/reg_test0 | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[15][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[5][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[12][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[0].u_ads1299_arrange/time_cnt[15]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[4][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[7][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 9 | 16 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[10][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[8][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 10 | 16 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[9][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 11 | 16 | 1.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[3][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[13][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/EN_O | | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[2][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[1][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[11][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[0][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[14][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_stim_config/eeg_send_package_num[15]_i_1_n_0 | u_pl_top/u_stim_config/eeg_emg_sel[1]_i_2_n_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_stim_config/emg_send_package_num[15]_i_1_n_0 | u_pl_top/u_stim_config/eeg_emg_sel[1]_i_2_n_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/crc16[15]_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/upload_round_qty | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[11][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/transmit_arrange[0].u_ads1299_arrange/time_cnt[15]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[5][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[10][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[2][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 8 | 16 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/transmit_arrange[1].u_ads1299_arrange/time_cnt[15]_i_1__0_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[8][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 10 | 16 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[6][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 7 | 16 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[7][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_im0_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_xfer_reg_ns | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_ch_cur[6][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 6 | 16 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 16 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/cur_thr[9][15]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 9 | 16 | 1.78 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 16 | 8.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/crc160 | u_pl_top/u0_upload_top/u_upload_protocol_intan/upload_round_qty_1 | 6 | 16 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BURST_WD_LEN_CONTROLLER/burst_wd[0]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 5 | 17 | 3.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr[16]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 5 | 17 | 3.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 17 | 5.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 17 | 4.25 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_iport1_o[0] | 5 | 17 | 3.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 17 | 4.25 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 5 | 17 | 3.40 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 17 | 4.25 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 4 | 17 | 4.25 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[0] | 3 | 18 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.s_axi_arid_d | | 5 | 18 | 3.60 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg[17]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 3 | 18 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.s_axi_awid_d | | 7 | 18 | 2.57 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 3 | 18 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[0] | 3 | 18 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 7 | 18 | 2.57 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 6 | 19 | 3.17 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[22]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 20 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 20 | 3.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[22]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 20 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 20 | 3.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 20 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 8 | 20 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 20 | 3.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[19]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[19]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[19]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[22]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 20 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/E[0] | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/SR[0] | 4 | 20 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[1] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 20 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 5 | 20 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 20 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 21 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 5 | 21 | 4.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 4 | 21 | 5.25 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/RST_AD5941/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SS[0] | 6 | 21 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/m_aruser | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 5 | 21 | 4.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 5 | 21 | 4.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 21 | 3.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 10 | 22 | 2.20 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 8 | 23 | 2.88 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_to_wsc_reg | | 3 | 23 | 7.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 3 | 23 | 7.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 12 | 23 | 1.92 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_to_wsc_reg | | 3 | 23 | 7.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[17][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[117][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 3 | 24 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[13][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[113][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[37][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[3][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/upload_ch[3][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[109][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[9][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[25][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[29][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[105][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[109][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[61][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 3 | 24 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[9][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[93][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 24 | 1.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[97][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[45][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[49][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[37][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[25][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[3][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[3][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[5][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 24 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/upload_ch[5][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/eeg_cr_r_reg[31]_1[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[21][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[77][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 24 | 1.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[93][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[101][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[5][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[61][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[57][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/E[0] | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[9][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[97][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 24 | 1.41 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[41][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[89][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[53][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[81][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[85][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[53][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[77][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[85][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[65][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[21][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[61][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[13][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[41][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[5][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[69][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[57][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[17][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[57][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[89][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[5][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 24 | 1.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[53][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[45][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/E[0] | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[73][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[33][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[65][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[37][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[3][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[49][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[41][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/upload_ch[5][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[17][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 24 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[61][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[49][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[9][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/areset_r | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[105][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_acq_collect/FSM_sequential_cstate_reg_n_0 | u_pl_top/u_cur_mon_top/u_acq_collect/FSM_sequential_cstate_i_2_n_0 | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[53][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/upload_ch[3][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/areset_r | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[81][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[101][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[13][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/rx_data_en | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[57][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[29][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[29][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[41][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[33][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/rx_data_en | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[29][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[33][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/areset_r | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[45][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[25][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 24 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[113][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[45][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[13][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[25][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[33][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[37][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/ch_mapping2pc[17][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[21][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 24 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[117][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[121][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/areset_r | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[125][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/ch_mapping2pc[21][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[121][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 24 | 1.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/pre_message[73][7]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 24 | 2.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[49][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[69][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/pre_message[125][7]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 24 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/SR[0] | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/areset | 11 | 25 | 2.27 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[52].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset | 11 | 25 | 2.27 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/FSM_onehot_cstate[2]_i_2_n_0 | 12 | 25 | 2.08 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CHANN_EN/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[49].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[50].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[51].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/SR[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[43].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/SR[0] | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[48].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[68].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[65].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[66].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[67].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[45].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[41].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[42].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[46].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[44].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[29].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[26].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[27].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[28].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[47].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[53].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[54].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[55].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[37].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[34].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[35].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[36].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[57].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[58].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[59].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[21].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[24].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[60].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[61].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[62].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[63].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[64].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[18].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[20].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[32].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[30].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[31].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[40].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[38].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[39].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[14].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/SR[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[56].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[0].u_ad7689_dual_if/m_axis_acq_tvalid | u_pl_top/u_cur_mon_top/u_acq_collect/FSM_sequential_cstate_i_2_n_0 | 7 | 25 | 3.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[69].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[70].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/areset | 10 | 25 | 2.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 26 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/acquisition[1].u_ad7689_dual_if/m_axis_acq_tvalid | u_pl_top/u_cur_mon_top/u_acq_collect/FSM_sequential_cstate_i_2_n_0 | 6 | 26 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_rd_en | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 4 | 26 | 6.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 26 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1_n_0 | 5 | 27 | 5.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/sig_coelsc_tag_reg0 | 5 | 27 | 5.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 10 | 27 | 2.70 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1_n_0 | 5 | 27 | 5.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 7 | 27 | 3.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 8 | 27 | 3.38 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 4 | 28 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg[27]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 4 | 28 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/ram_rd_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rst_d1_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/ram_rd_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_3/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rst_d1_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/ram_rd_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rst_d1_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_wr_rst_ic_reg_0 | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 8 | 31 | 3.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 9 | 31 | 3.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 7 | 31 | 4.43 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[28]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1_n_0 | 7 | 31 | 4.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_7[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_47[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_43[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_28[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_48[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_45[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_25[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_42[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_49[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_r_node_6/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/s_sc_valid | | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_44[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_46[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_5[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_50[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_51[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_22[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_50[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_40[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_48[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_33[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_6[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_9[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_61[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_60[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_59[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_58[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_29[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_55[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_25[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_54[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_41[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_32[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_21[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_13[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_30[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_42[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_12[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_15[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_40[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/E[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 23 | 32 | 1.39 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_53[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_12[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_26[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/upload_round_qty_set[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_3[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_31[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 21 | 32 | 1.52 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_34[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_10[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_23[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 18 | 32 | 1.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_36[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_52[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_16[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/upload_bytes_cnt[31]_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_54[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_1[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/upload_round_qty_1 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_43[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/thr_total_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1][0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_11[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_1[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_0[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/E[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_2[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/test_data[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_24[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_28[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_41[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/package_id[0]_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_39[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/thr_pos_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_53[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 22 | 32 | 1.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_55[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_32[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 20 | 32 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_56[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_21[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_57[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_58[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_59[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1][0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 21 | 32 | 1.52 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_11[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_0[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_13[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_18[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_14[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 23 | 32 | 1.39 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_17[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_10[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_20[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_27[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/thr_neg_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_61[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_8[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_9[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_7[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_6[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_60[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id[0]_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/upload_bytes_cnt[31]_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/test_data[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/upload_record_bytes_cnt[31]_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/upload_round_qty_1 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_intan/upload_rounds_cnt[31]_i_1__0_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/package_id[0]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/upload_bytes_cnt[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/upload_record_bytes_cnt[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/upload_rounds_cnt[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_protocol_ql/upload_round_qty | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_mon_config/bram_dout[31]_i_3_n_0 | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_upload/p_0_in | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/record_tx0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_config/test_data[31]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/bram_dout[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_16[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_14[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 19 | 32 | 1.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_total_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_pos_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_34[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_45[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_29[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_27[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_22[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_24[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/cnv_res_tdata0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_26[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/package_overtime_ms[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_51[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_5[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_cur_monitor/flt_neg_cur[31]_i_1_n_0 | u_pl_top/u_cur_mon_top/u_cur_monitor/interrupt_i_3_n_0 | 10 | 32 | 3.20 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0 | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_30[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 20 | 32 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_18[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/package_id[0]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/upload_bytes_cnt[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_23[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_2[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_19[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_37[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_38[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_57[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_31[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/upload_round_qty | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/upload_record_bytes_cnt[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_56[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_ql/upload_rounds_cnt[31]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_4[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_20[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 32 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_49[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_52[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 21 | 32 | 1.52 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_36[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_3[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_8[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/record_tx0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_44[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_35[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_46[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_39[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_17[0] | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_r_node_3/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_config/eeg_tr_r[0][31]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_upload/FSM_onehot_cstate_reg_n_0_[2] | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_r_node_2/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/upload_record_bytes_cnt[31]_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_stim_config/bram_rd_valid | u_pl_top/u_stim_config/eeg_emg_sel[1]_i_2_n_0 | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_r_node_1/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_stim_config/test_data[31]_i_1_n_0 | u_pl_top/u_stim_config/eeg_emg_sel[1]_i_2_n_0 | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/bram_dout[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_protocol_intan/upload_rounds_cnt[31]_i_1__0_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/package_overtime_ms[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/cnv_res_tdata0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/u_eeg_config/bram_dout[31]_i_1_n_0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/trans_if[1].u_ads1299_if/cnv_res_tdata0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/eeg_tr_r[0][31]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/eeg_tr_r | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/bram_dout[31]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_config/test_data[31]_i_1_n_0 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/test_data[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/upload_round_qty_set[31]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_33[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/s_axi_rdata_i[31]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_37[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 17 | 32 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_47[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_19[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 20 | 32 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_38[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_15[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 21 | 32 | 1.52 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_r_node_0/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_35[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_4[0] | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 15 | 32 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/shift_en_o | | 8 | 33 | 4.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/shift_en_o | | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[13].mu_srl_reg/shift_en_o | | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shift_en_o | | 8 | 33 | 4.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[23].mu_srl_reg/shift_en_o | | 10 | 33 | 3.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/shift_en_o | | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_r_node_7/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/s_sc_valid | | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shift_en_o | | 10 | 33 | 3.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_r_node_5/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 10 | 33 | 3.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_r_node_4/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/E[0] | | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shift_en_o | | 7 | 33 | 4.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[15].mu_srl_reg/shift_en_o | | 7 | 33 | 4.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_den_o | | 12 | 33 | 2.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_upload/round_end1 | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 8 | 33 | 4.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shift_en_o | | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/E[0] | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shift_en_o | | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_eeg_top/u_eeg_upload/p_5_out | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 7 | 33 | 4.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/gen_rsplitter.artrans_cntr | | 10 | 34 | 3.40 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[1]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 9 | 34 | 3.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/gen_wsplitter.awtrans_cntr | | 11 | 34 | 3.09 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_2/i_w_node_2/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 12 | 35 | 2.92 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_input_cache_type_reg0 | 9 | 35 | 3.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_input_cache_type_reg0 | 9 | 35 | 3.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_input_cache_type_reg0 | 9 | 35 | 3.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_lsh_im0[15]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 11 | 36 | 3.27 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_2[0] | 7 | 36 | 5.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_ad7689_dual_ctrl/clk_cnt[31]_i_2_n_0 | 12 | 36 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 12 | 36 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 11 | 36 | 3.27 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_3[0] | 11 | 36 | 3.27 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 13 | 36 | 2.77 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_3[0] | 5 | 36 | 7.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/m_vector_i | | 8 | 37 | 4.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i | | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer[2052]_i_1_n_0 | | 8 | 37 | 4.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/m_vector_i | | 5 | 37 | 7.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i | | 5 | 37 | 7.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 11 | 37 | 3.36 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_4/i_w_node_4/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 16 | 37 | 2.31 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 8 | 37 | 4.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 8 | 37 | 4.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 13 | 37 | 2.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 13 | 37 | 2.85 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 10 | 37 | 3.70 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[1136]_i_1__0_n_0 | | 11 | 38 | 3.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i | | 8 | 38 | 4.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_7/i_w_node_7/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[62]_i_1_n_0 | | 8 | 38 | 4.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_6/i_w_node_6/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[62]_i_1_n_0 | | 11 | 38 | 3.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 8 | 39 | 4.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_3/i_w_node_3/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 11 | 39 | 3.55 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_5/i_w_node_5/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 8 | 39 | 4.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/Z_IO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SS[0] | 12 | 39 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 9 | 39 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/Rst_to_spi | 8 | 39 | 4.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_0/i_w_node_0/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 10 | 39 | 3.90 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.sckt_wr_rst_ic_reg_0 | 7 | 39 | 5.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes_1/i_w_node_1/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.inst_cntr/E[0] | | 9 | 39 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/GEN_INDET_BTT.lsig_absorb2tlast_reg | 10 | 40 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_btt_cntr0 | 11 | 40 | 3.64 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/gpio_core_1/Read_Reg_Rst | 7 | 40 | 5.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/GEN_INDET_BTT.lsig_absorb2tlast_reg | 11 | 40 | 3.64 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 13 | 41 | 3.15 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 10 | 41 | 4.10 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 14 | 41 | 2.93 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 9 | 41 | 4.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 9 | 41 | 4.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 13 | 41 | 3.15 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 10 | 42 | 4.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 9 | 42 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 9 | 42 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 8 | 42 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 11 | 42 | 3.82 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1136]_i_1_n_0 | | 9 | 42 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1144]_i_1_n_0 | | 9 | 42 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 10 | 42 | 4.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 6 | 42 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_reg_stall/m_vector_i | | 7 | 43 | 6.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1_n_0 | | 7 | 43 | 6.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/m_vector_i | | 8 | 43 | 5.38 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_reg_stall/m_vector_i | | 9 | 43 | 4.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 6 | 43 | 7.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/m_vector_i | | 9 | 43 | 4.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1_n_0 | | 10 | 43 | 4.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 6 | 43 | 7.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1_n_0 | | 8 | 43 | 5.38 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/skid_buffer[1144]_i_1__0_n_0 | | 8 | 43 | 5.38 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/GPIO/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 10 | 43 | 4.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 6 | 43 | 7.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/m_vector_i | | 8 | 44 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__0_n_0 | | 7 | 44 | 6.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__0_n_0 | | 7 | 44 | 6.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/m_vector_i | | 9 | 44 | 4.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__0_n_0 | | 6 | 44 | 7.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/m_vector_i | | 8 | 44 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 11 | 44 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 9 | 44 | 4.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 13 | 44 | 3.38 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_ok_to_post_rd_addr_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1_n_0 | 8 | 45 | 5.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 9 | 46 | 5.11 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 9 | 46 | 5.11 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1_n_0 | 8 | 46 | 5.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1_n_0 | 8 | 46 | 5.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 7 | 46 | 6.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/m_sc_areset_r | 10 | 46 | 4.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 18 | 47 | 2.61 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/shift_en_o | | 10 | 49 | 4.90 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[25].mu_srl_reg/shift_en_o | | 12 | 49 | 4.08 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/m_vector_i | | 9 | 49 | 5.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid_buffer[1144]_i_1__2_n_0 | | 9 | 49 | 5.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/skid_buffer[1144]_i_1__1_n_0 | | 10 | 49 | 4.90 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/m_vector_i | | 8 | 49 | 6.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/shift_en_o | | 9 | 49 | 5.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/shift_en_o | | 8 | 49 | 6.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.I_S2MM_CMDSTS/GEN_HOLD_NO_DATA.s_axis_s2mm_cmd_tvalid_reg_0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 9 | 53 | 5.89 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.I_S2MM_CMDSTS/dmacr_i_reg[2] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 10 | 53 | 5.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.I_S2MM_CMDSTS/GEN_HOLD_NO_DATA.s_axis_s2mm_cmd_tvalid_reg_0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 13 | 53 | 4.08 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 21 | 53 | 2.52 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_1 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 11 | 53 | 4.82 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 10 | 54 | 5.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 11 | 54 | 4.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 11 | 54 | 4.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 9 | 54 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[1144]_i_1__0_n_0 | | 16 | 55 | 3.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[1144]_i_1_n_0 | | 12 | 55 | 4.58 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 22 | 59 | 2.68 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 25 | 59 | 2.36 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/m_vector_i | | 22 | 61 | 2.77 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/m_vector_i | | 19 | 61 | 3.21 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 23 | 63 | 2.74 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_run_time/pulse_ms | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/pulse_ms_reg | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/pulse_ms_reg | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u0_upload_top/u_upload_sort/ch_list[63]_i_1_n_0 | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 13 | 64 | 4.92 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_upload_sort/ch_list[63]_i_1_n_0 | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 10 | 64 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u1_upload_top/u_run_time/pulse_ms | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
|
|
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | | 24 | 65 | 2.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 15 | 71 | 4.73 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 15 | 71 | 4.73 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u1_eeg_top/trans_if[0].u_ads1299_if1/u_ads1299_spi1/bbstub_peripheral_aresetn[0] | 24 | 72 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 17 | 73 | 4.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 20 | 73 | 3.65 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/reset2ip_reset_int | 18 | 73 | 4.06 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 23 | 74 | 3.22 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u0_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 41 | 77 | 1.88 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u1_upload_top/u_upload_sort/bbstub_peripheral_aresetn[0] | 36 | 77 | 2.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 16 | 81 | 5.06 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 16 | 81 | 5.06 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 17 | 81 | 4.76 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/m_sc_areset_r | 16 | 81 | 5.06 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/shift_en_o | | 16 | 89 | 5.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]_i_2_n_0 | 39 | 92 | 2.36 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_cur_monitor/sclr | 24 | 96 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/DECODER_INST/E[0] | | 40 | 97 | 2.42 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_srl_fff/shift_en_o | | 26 | 103 | 3.96 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u0_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/bbstub_peripheral_aresetn[0] | 39 | 129 | 3.31 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[0] | 79 | 168 | 2.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_cur_mon_top/u_vio_cur_flt_state/inst/PROBE_IN_INST/read_done | 62 | 194 | 3.13 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | | 1741 | 7154 | 4.11 |
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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