2002 lines
268 KiB
Plaintext
2002 lines
268 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Thu Sep 3 09:05:00 2026
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# Process ID: 19892
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# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v4
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent44252 D:\Project\spinal_stim\pl\spinal_stim_v4\c64_pro.xpr
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# Log file: D:/Project/spinal_stim/pl/spinal_stim_v4/vivado.log
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# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v4\vivado.jou
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# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
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#-----------------------------------------------------------
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start_gui
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open_project D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.3 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.3/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
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open_project: Time (s): cpu = 00:00:53 ; elapsed = 00:00:33 . Memory (MB): peak = 2725.547 ; gain = 569.848
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launch_simulation
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Command: launch_simulation
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INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
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WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
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INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
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INFO: [USF-XSim-7] Finding pre-compiled libraries...
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INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2798.551 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
|
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Starting simulation data flow analysis
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|
Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
|
|
Compiling module xil_defaultlib.ads1299_if
|
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
|
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
|
|
Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
|
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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|
Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
|
|
Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
|
|
Compiling module unisims_ver.GND
|
|
Compiling module unisims_ver.FDRE_default
|
|
Compiling module unisims_ver.CARRY4
|
|
Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
|
|
Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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|
Compiling module unisims_ver.LUT5
|
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Compiling module unisims_ver.LUT6
|
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Compiling module unisims_ver.LUT4
|
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Compiling module unisims_ver.x_lut1_mux2
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|
Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
|
|
Compiling module unisims_ver.LUT3
|
|
Compiling module unisims_ver.MUXF8
|
|
Compiling module unisims_ver.MUXF7
|
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Compiling module xil_defaultlib.vio_cur_flt_state
|
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
|
|
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
|
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Compiling module unisims_ver.FDSE_default
|
|
Compiling module unisims_ver.SRL16E_default
|
|
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
|
|
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
|
|
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
|
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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|
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
|
|
Compiling module xil_defaultlib.fifo_generator_1
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|
Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
|
|
Compiling module xil_defaultlib.accel_top
|
|
Compiling module xil_defaultlib.run_time_default
|
|
Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
|
|
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
|
|
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
|
|
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
|
|
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
|
|
Compiling module xil_defaultlib.axis_data_fifo_w8_d128
|
|
Compiling module xil_defaultlib.upload_sort_default
|
|
Compiling module xil_defaultlib.upload_protocol_ql_default
|
|
Compiling module xil_defaultlib.upload_protocol_intan
|
|
Compiling module xil_defaultlib.upload_top
|
|
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
|
|
Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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|
Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
|
|
Compiling module xil_defaultlib.fifo_generator_0
|
|
Compiling module xil_defaultlib.eeg_emg_upload
|
|
Compiling module xil_defaultlib.stim_config
|
|
Compiling module xil_defaultlib.pl_top
|
|
Compiling module xil_defaultlib.rhs2116_mod
|
|
Compiling module xil_defaultlib.ads1299_mod
|
|
Compiling module xil_defaultlib.pl_top_tb
|
|
Compiling module xil_defaultlib.glbl
|
|
Built simulation snapshot pl_top_tb_behav
|
|
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:28 . Memory (MB): peak = 2798.551 ; gain = 0.000
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '28' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
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INFO: [USF-XSim-98] *** Running xsim
|
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
|
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
|
|
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
|
|
There are no instances of module "bd_6e35" in the design.
|
|
|
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
|
|
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
|
|
There are no instances of module "bd_962a" in the design.
|
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|
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
|
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
|
|
There are no instances of module "design_a9_1" in the design.
|
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|
|
Time resolution is 1 ps
|
|
open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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|
source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
|
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# add_wave /
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# set_property needs_save false [current_wave_config]
|
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
|
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# }
|
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2819.309 ; gain = 20.758
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:59 ; elapsed = 00:01:19 . Memory (MB): peak = 2819.309 ; gain = 29.266
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/clk}} {{/pl_top_tb/DUT/u1_eeg_top/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/bram_addr}} {{/pl_top_tb/DUT/u1_eeg_top/bram_clk}} {{/pl_top_tb/DUT/u1_eeg_top/bram_din}} {{/pl_top_tb/DUT/u1_eeg_top/bram_dout}} {{/pl_top_tb/DUT/u1_eeg_top/bram_en}} {{/pl_top_tb/DUT/u1_eeg_top/bram_rst}} {{/pl_top_tb/DUT/u1_eeg_top/bram_we}} {{/pl_top_tb/DUT/u1_eeg_top/interrupt}} {{/pl_top_tb/DUT/u1_eeg_top/axis_record_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/axis_record_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/axis_record_tready}} {{/pl_top_tb/DUT/u1_eeg_top/axis_record_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/cs}} {{/pl_top_tb/DUT/u1_eeg_top/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/miso}} {{/pl_top_tb/DUT/u1_eeg_top/drdy}} {{/pl_top_tb/DUT/u1_eeg_top/start}} {{/pl_top_tb/DUT/u1_eeg_top/debug_sig}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_er}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_cr}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_sr}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_tr_array}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_rr_array}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_sr_r_evt}} {{/pl_top_tb/DUT/u1_eeg_top/cs_w}} {{/pl_top_tb/DUT/u1_eeg_top/send_enable}} {{/pl_top_tb/DUT/u1_eeg_top/send_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/send_length}} {{/pl_top_tb/DUT/u1_eeg_top/send_data_array}} {{/pl_top_tb/DUT/u1_eeg_top/recv_data_array}} {{/pl_top_tb/DUT/u1_eeg_top/recv_data_en_array}} {{/pl_top_tb/DUT/u1_eeg_top/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_start}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_drdy}} {{/pl_top_tb/DUT/u1_eeg_top/upload_round}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tready}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tdata_array}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tlast_array}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tready_array}} {{/pl_top_tb/DUT/u1_eeg_top/cnv_res_tvalid_array}} {{/pl_top_tb/DUT/u1_eeg_top/record_enable}} {{/pl_top_tb/DUT/u1_eeg_top/CLK_PERIOD}} {{/pl_top_tb/DUT/u1_eeg_top/CHIPSET_QTY}} {{/pl_top_tb/DUT/u1_eeg_top/CHIPSET_CH_QTY}} {{/pl_top_tb/DUT/u1_eeg_top/SPIS_QTY}} {{/pl_top_tb/DUT/u1_eeg_top/SPI_SLAVE_QTY}} {{/pl_top_tb/DUT/u1_eeg_top/SPI_CLK_DIV}} {{/pl_top_tb/DUT/u1_eeg_top/SPI_DATA_WIDTH}} {{/pl_top_tb/DUT/u1_eeg_top/SPI_TRANS_PERIOD}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:49 ; elapsed = 00:02:10 . Memory (MB): peak = 3488.348 ; gain = 669.039
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:20 ; elapsed = 00:00:52 . Memory (MB): peak = 3488.348 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/emg_ads1299_spi_cs}} {{/pl_top_tb/DUT/emg_ads1299_spi_sclk}} {{/pl_top_tb/DUT/emg_ads1299_spi_mosi}} {{/pl_top_tb/DUT/emg_ads1299_spi_miso}} {{/pl_top_tb/DUT/emg_ads1299_drdy_n}} {{/pl_top_tb/DUT/emg_ads1299_start}} {{/pl_top_tb/DUT/emg_ads1299_reset_n}} {{/pl_top_tb/DUT/emg_ads1299_pwdn_n}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:31 . Memory (MB): peak = 3488.348 ; gain = 0.000
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save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
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close_sim
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INFO: xsimkernel Simulation Memory Usage: 30676 KB (Peak: 30676 KB), Simulation CPU Usage: 212640 ms
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INFO: [Simtcl 6-16] Simulation closed
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launch_simulation
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Command: launch_simulation
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INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
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WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
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INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
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INFO: [USF-XSim-7] Finding pre-compiled libraries...
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INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 3488.348 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:515]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:626]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:632]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:642]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:678]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:684]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:696]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
|
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Compiling module unisims_ver.GND
|
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Compiling module unisims_ver.FDRE_default
|
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
|
|
Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:30 . Memory (MB): peak = 3488.348 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '30' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 3488.348 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:50 ; elapsed = 00:01:23 . Memory (MB): peak = 3488.348 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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|
run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 3488.348 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
|
|
save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
|
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close_sim
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|
INFO: xsimkernel Simulation Memory Usage: 25752 KB (Peak: 25752 KB), Simulation CPU Usage: 26171 ms
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INFO: [Simtcl 6-16] Simulation closed
|
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reset_run synth_1
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launch_runs synth_1 -jobs 20
|
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[Thu Sep 3 09:20:43 2026] Launched synth_1...
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Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
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open_run synth_1 -name synth_1
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Design is defaulting to impl run constrset: constrs_1
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Design is defaulting to synth run part: xc7z020clg400-2
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INFO: [Device 21-403] Loading part xc7z020clg400-2
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.dcp' for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp' for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32.dcp' for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.dcp' for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3517.699 ; gain = 29.352
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INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Chipscope 16-324] Core: u_pl_top/u_cur_mon_top/u_vio_cur_flt_state UUID: 8a67dbc2-bda6-5e4b-b982-bb6511a2b4be
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc:50]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
INFO: [Project 1-1714] 477 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 4418.535 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 188 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 27 instances
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 3 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 144 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 14 instances
|
|
|
|
open_run: Time (s): cpu = 00:01:03 ; elapsed = 00:00:48 . Memory (MB): peak = 4467.109 ; gain = 978.762
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
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create_debug_port u_ila_0 probe
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
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create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
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|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/emg_ads1299_spi_cs ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/emg_ads1299_spi_miso ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/emg_ads1299_spi_mosi ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/emg_ads1299_spi_sclk ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/emg_ads1299_spi_sclk_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_rst ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/in004_out ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
|
connect_debug_port u_ila_0/probe65 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
|
connect_debug_port u_ila_0/probe66 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
|
connect_debug_port u_ila_0/probe67 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
|
|
connect_debug_port u_ila_0/probe68 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
|
|
connect_debug_port u_ila_0/probe69 [get_nets [list mux_pwr_en_OBUF ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
|
|
connect_debug_port u_ila_0/probe70 [get_nets [list u_pl_top/stop_sample ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
|
|
[Thu Sep 3 09:30:56 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
|
|
[Thu Sep 3 09:30:56 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/runme.log
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
INFO: [Project 1-1918] Creating Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa ...
|
|
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
|
|
INFO: [Project 1-1941] Successfully created Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2023.1/data/embeddedsw) loading 0 seconds
|
|
write_hw_platform: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 4630.340 ; gain = 116.602
|
|
launch_simulation
|
|
Command: launch_simulation
|
|
INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
|
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 4652.398 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:515]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:626]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:632]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:642]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:678]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:684]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:696]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
|
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
|
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Compiling module unisims_ver.GND
|
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:05 ; elapsed = 00:00:23 . Memory (MB): peak = 4652.465 ; gain = 0.066
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INFO: [USF-XSim-69] 'elaborate' step finished in '23' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 4661.031 ; gain = 8.566
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:52 ; elapsed = 00:01:16 . Memory (MB): peak = 4661.031 ; gain = 30.691
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:31 ; elapsed = 00:02:08 . Memory (MB): peak = 4858.625 ; gain = 197.594
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/u1_ads1299_mod/cs}} {{/pl_top_tb/u1_ads1299_mod/sclk}} {{/pl_top_tb/u1_ads1299_mod/mosi}} {{/pl_top_tb/u1_ads1299_mod/miso}} {{/pl_top_tb/u1_ads1299_mod/drdy}} {{/pl_top_tb/u1_ads1299_mod/start}} {{/pl_top_tb/u1_ads1299_mod/clk}} {{/pl_top_tb/u1_ads1299_mod/rst_n}} {{/pl_top_tb/u1_ads1299_mod/serial_in}} {{/pl_top_tb/u1_ads1299_mod/rx_cnt}} {{/pl_top_tb/u1_ads1299_mod/rx_data}} {{/pl_top_tb/u1_ads1299_mod/tx_cnt}} {{/pl_top_tb/u1_ads1299_mod/reg_data}} {{/pl_top_tb/u1_ads1299_mod/cnv_data}} {{/pl_top_tb/u1_ads1299_mod/start_t_cnt}} {{/pl_top_tb/u1_ads1299_mod/cnv_en}} {{/pl_top_tb/u1_ads1299_mod/r_cnt}} {{/pl_top_tb/u1_ads1299_mod/DATA_WIDTH}} {{/pl_top_tb/u1_ads1299_mod/WIRE_DELAY}} {{/pl_top_tb/u1_ads1299_mod/T_CLK}} {{/pl_top_tb/u1_ads1299_mod/RDATAC}} {{/pl_top_tb/u1_ads1299_mod/SDATAC}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 1 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 5518.340 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
|
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run 1 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 5518.340 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /clk}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /rst_n}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
|
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run 1 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 5518.340 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /drdy}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 5518.340 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CLK_PERIOD}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CLK_DIV}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/DATA_WIDTH}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/NO_OF_SLAVES}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CNT_POS}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CNT_NEG}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/T_SCCS}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/T_SCH}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/IDLE}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/TRANS_ST}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/SCCS_ST}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CSH_ST}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 5518.340 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/clk}} {{/pl_top_tb/DUT/u1_eeg_top/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/eeg_cr}} {{/pl_top_tb/DUT/u1_eeg_top/send_enable}} {{/pl_top_tb/DUT/u1_eeg_top/send_cs_n}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /rdatac_enable}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_start}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_drdy}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_drdy_r}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /drdy}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tvalid}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cs_n}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /nstate}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 5518.340 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cnt}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 5518.340 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tready}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 5581.402 ; gain = 0.000
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run 0.5 ms
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run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 5581.402 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 0.5 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 5581.402 ; gain = 0.000
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run 0.5 ms
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run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 5581.402 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CLK_PERIOD}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CLK_DIV}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/DATA_WIDTH}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/NO_OF_SLAVES}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CNT_POS}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CNT_NEG}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/T_SCCS}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/T_SCH}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/IDLE}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/TRANS_ST}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/SCCS_ST}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/CSH_ST}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /send_enable}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /rdatac_enable}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_start}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /time_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /t_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /cnv_drdy_r}} {{/pl_top_tb/DUT/u1_eeg_top/\transmit_arrange[0].u_ads1299_arrange /drdy}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/nstate}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/tx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/rx_data}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/clk_en}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_pos}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sck_neg}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/trans_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/slv_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/sclk_r}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/cs_release}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sccs_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/t_sch_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /u_ads1299_spi/read_flag}}
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save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
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close_sim
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INFO: xsimkernel Simulation Memory Usage: 30840 KB (Peak: 30840 KB), Simulation CPU Usage: 211702 ms
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INFO: [Simtcl 6-16] Simulation closed
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exit
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INFO: [Common 17-206] Exiting Vivado at Fri Sep 4 09:07:49 2026...
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