2550 lines
406 KiB
Plaintext
2550 lines
406 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Tue Sep 1 10:12:21 2026
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# Process ID: 13756
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# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v4
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3664 D:\Project\spinal_stim\pl\spinal_stim_v4\c64_pro.xpr
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# Log file: D:/Project/spinal_stim/pl/spinal_stim_v4/vivado.log
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# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v4\vivado.jou
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# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
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#-----------------------------------------------------------
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start_gui
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open_project D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.3 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.3/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
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open_project: Time (s): cpu = 00:00:54 ; elapsed = 00:00:35 . Memory (MB): peak = 2726.102 ; gain = 584.547
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exit
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INFO: [Common 17-206] Exiting Vivado at Tue Sep 1 10:13:26 2026...
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reset_run synth_1
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launch_runs synth_1 -jobs 20
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[Tue Sep 1 10:19:26 2026] Launched synth_1...
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Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
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close_design
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open_run synth_1 -name synth_1
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Design is defaulting to impl run constrset: constrs_1
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Design is defaulting to synth run part: xc7z020clg400-2
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.dcp' for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp' for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32.dcp' for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.dcp' for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 4569.504 ; gain = 0.000
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INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Chipscope 16-324] Core: u_pl_top/u_cur_mon_top/u_vio_cur_flt_state UUID: 8a67dbc2-bda6-5e4b-b982-bb6511a2b4be
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc:50]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
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WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
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|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
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|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
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INFO: [Project 1-1714] 477 XPM XDC files have been applied to the design.
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 4569.504 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
|
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A total of 188 instances were transformed.
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IOBUF => IOBUF (IBUF, OBUFT): 27 instances
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RAM16X1D => RAM32X1D (RAMD32(x2)): 3 instances
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RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 144 instances
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RAM32X1D => RAM32X1D (RAMD32(x2)): 14 instances
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open_run: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 4635.828 ; gain = 66.324
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create_debug_core u_ila_0 ila
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
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set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
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create_debug_port u_ila_0 probe
|
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set_property port_width 32 [get_debug_ports u_ila_0/probe1]
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
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create_debug_port u_ila_0 probe
|
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set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
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connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
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create_debug_port u_ila_0 probe
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
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connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
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create_debug_port u_ila_0 probe
|
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
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connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
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create_debug_port u_ila_0 probe
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
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create_debug_port u_ila_0 probe
|
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set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/in001_out ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list mux_pwr_en_OBUF ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/stop_sample ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
|
|
[Tue Sep 1 10:27:53 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
|
|
[Tue Sep 1 10:27:53 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/runme.log
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
INFO: [Project 1-1918] Creating Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa ...
|
|
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
|
|
INFO: [Project 1-1941] Successfully created Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
write_hw_platform: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 4721.582 ; gain = 46.836
|
|
open_hw_manager
|
|
connect_hw_server -allow_non_jtag
|
|
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
|
INFO: [Labtools 27-2222] Launching hw_server...
|
|
INFO: [Labtools 27-2221] Launch Output:
|
|
|
|
****** Xilinx hw_server v2023.1
|
|
**** Build date : May 7 2023 at 15:26:57
|
|
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
|
|
|
|
|
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
|
|
INFO: [Labtools 27-3417] Launching cs_server...
|
|
INFO: [Labtools 27-2221] Launch Output:
|
|
|
|
|
|
******** Xilinx cs_server v2023.1.0
|
|
****** Build date : Apr 10 2023-23:59:24
|
|
**** Build number : 2023.1.1681142364
|
|
** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
|
|
** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
|
|
|
|
|
|
|
|
connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:09 . Memory (MB): peak = 4737.832 ; gain = 0.000
|
|
open_hw_target
|
|
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
|
|
set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
|
|
set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
|
|
current_hw_device [get_hw_devices xc7z020_1]
|
|
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
|
|
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
|
|
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
|
|
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/axis_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 13:34:43
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 13:34:43
|
|
INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
|
|
display_hw_ila_data: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 4939.102 ; gain = 0.000
|
|
set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 13:35:01
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 13:35:29
|
|
INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
|
|
display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4939.102 ; gain = 0.000
|
|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 13:36:08
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
|
|
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 13:36:08
|
|
INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
|
|
display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 4939.102 ; gain = 0.000
|
|
launch_simulation
|
|
Command: launch_simulation
|
|
INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/sim/design_a9_1_processing_system7_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_processing_system7_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/sim/axis_data_fifo_w8_d128.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w8_d128
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module fifo_generator_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module fifo_generator_1
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_gray
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_gray__2
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_single
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_single__2
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_xpm_cdc_sync_rst__2
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_generic_cstr
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_prim_width
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_prim_wrapper
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_top
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_v8_4_6
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_blk_mem_gen_v8_4_6_synth
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_clk_x_pntrs
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_compare
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_compare_0
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_compare_1
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_compare_2
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_fifo_generator_ramfifo
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_fifo_generator_top
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_fifo_generator_v13_2_8
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_fifo_generator_v13_2_8_synth
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_memory
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_rd_bin_cntr
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_rd_logic
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_rd_status_flags_as
|
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_reset_blk_ramfifo
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_wr_bin_cntr
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_wr_logic
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INFO: [VRFC 10-311] analyzing module fifo_generator_1_wr_status_flags_as
|
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INFO: [VRFC 10-311] analyzing module glbl
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state
|
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state_vio_v3_0_23_decoder
|
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state_vio_v3_0_23_probe_in_one
|
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state_vio_v3_0_23_probe_width
|
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state_vio_v3_0_23_vio
|
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INFO: [VRFC 10-311] analyzing module vio_cur_flt_state_xsdbs_v1_0_2_xsdbs
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_addsub_v12_0_15
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_addsub_v12_0_15_fabric_legacy
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_addsub_v12_0_15_legacy
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_addsub_v12_0_15_lut6_legacy
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_addsub_v12_0_15_viv
|
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INFO: [VRFC 10-311] analyzing module c_add_s16_s32_c_reg_fd_v12_0_6_viv
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/sim/design_a9_1_axis_data_fifo_2_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_axis_data_fifo_2_0
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/sim/design_a9_1_axis_data_fifo_1_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_axis_data_fifo_1_1
|
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_0/sim/bd_6e35_one_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_one_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_2/sim/bd_6e35_arinsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_3/sim/bd_6e35_rinsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_4/sim/bd_6e35_awinsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_5/sim/bd_6e35_winsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_6/sim/bd_6e35_binsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_7/sim/bd_6e35_arni_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_8/sim/bd_6e35_rni_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_9/sim/bd_6e35_awni_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_10/sim/bd_6e35_wni_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_11/sim/bd_6e35_bni_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_12/sim/bd_6e35_arni_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_1
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_13/sim/bd_6e35_rni_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_1
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_14/sim/bd_6e35_awni_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_1
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_15/sim/bd_6e35_wni_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_1
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_16/sim/bd_6e35_bni_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_1
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_17/sim/bd_6e35_arni_2.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_2
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_18/sim/bd_6e35_rni_2.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_2
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_19/sim/bd_6e35_awni_2.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_2
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_20/sim/bd_6e35_wni_2.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_2
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_21/sim/bd_6e35_bni_2.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_2
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_22/sim/bd_6e35_arni_3.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_23/sim/bd_6e35_rni_3.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_24/sim/bd_6e35_awni_3.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_25/sim/bd_6e35_wni_3.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_26/sim/bd_6e35_bni_3.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_27/sim/bd_6e35_arni_4.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_28/sim/bd_6e35_rni_4.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_29/sim/bd_6e35_awni_4.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_30/sim/bd_6e35_wni_4.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_31/sim/bd_6e35_bni_4.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_32/sim/bd_6e35_arni_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_33/sim/bd_6e35_rni_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_34/sim/bd_6e35_awni_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_35/sim/bd_6e35_wni_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_36/sim/bd_6e35_bni_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_37/sim/bd_6e35_arni_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_38/sim/bd_6e35_rni_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_39/sim/bd_6e35_awni_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_40/sim/bd_6e35_wni_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_41/sim/bd_6e35_bni_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_42/sim/bd_6e35_arni_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arni_7
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_43/sim/bd_6e35_rni_7.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_rni_7
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_44/sim/bd_6e35_awni_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awni_7
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_45/sim/bd_6e35_wni_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_wni_7
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_46/sim/bd_6e35_bni_7.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_bni_7
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_47/sim/bd_6e35_arinsw_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_1
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_48/sim/bd_6e35_rinsw_1.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_1
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_49/sim/bd_6e35_awinsw_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_1
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_50/sim/bd_6e35_winsw_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_1
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_51/sim/bd_6e35_binsw_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_1
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_52/sim/bd_6e35_arinsw_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_2
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_53/sim/bd_6e35_rinsw_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_2
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_54/sim/bd_6e35_awinsw_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_2
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_55/sim/bd_6e35_winsw_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_2
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_56/sim/bd_6e35_binsw_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_2
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_57/sim/bd_6e35_arinsw_3.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_58/sim/bd_6e35_rinsw_3.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_59/sim/bd_6e35_awinsw_3.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_60/sim/bd_6e35_winsw_3.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_61/sim/bd_6e35_binsw_3.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_62/sim/bd_6e35_arinsw_4.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_4
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_63/sim/bd_6e35_rinsw_4.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_4
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_64/sim/bd_6e35_awinsw_4.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_4
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_65/sim/bd_6e35_winsw_4.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_4
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_66/sim/bd_6e35_binsw_4.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_4
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_67/sim/bd_6e35_arinsw_5.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_5
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_68/sim/bd_6e35_rinsw_5.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_5
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_69/sim/bd_6e35_awinsw_5.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_70/sim/bd_6e35_winsw_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_71/sim/bd_6e35_binsw_5.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_5
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_72/sim/bd_6e35_arinsw_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_73/sim/bd_6e35_rinsw_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_74/sim/bd_6e35_awinsw_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_75/sim/bd_6e35_winsw_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_76/sim/bd_6e35_binsw_6.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_6
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_77/sim/bd_6e35_arinsw_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_7
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_78/sim/bd_6e35_rinsw_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_7
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_79/sim/bd_6e35_awinsw_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_7
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_80/sim/bd_6e35_winsw_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_7
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_81/sim/bd_6e35_binsw_7.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_7
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_82/sim/bd_6e35_arinsw_8.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_arinsw_8
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_83/sim/bd_6e35_rinsw_8.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_rinsw_8
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_84/sim/bd_6e35_awinsw_8.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_awinsw_8
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_85/sim/bd_6e35_winsw_8.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_winsw_8
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_86/sim/bd_6e35_binsw_8.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_binsw_8
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_87/sim/bd_6e35_s00mmu_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_s00mmu_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_88/sim/bd_6e35_s00tr_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_s00tr_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_89/sim/bd_6e35_s00sic_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_s00sic_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_90/sim/bd_6e35_s00a2s_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_s00a2s_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_91/sim/bd_6e35_sarn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_sarn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_92/sim/bd_6e35_srn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_srn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_93/sim/bd_6e35_sawn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_sawn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_94/sim/bd_6e35_swn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_swn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_95/sim/bd_6e35_sbn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_sbn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_96/sim/bd_6e35_m00s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_97/sim/bd_6e35_m00arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00arn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_98/sim/bd_6e35_m00rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00rn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_99/sim/bd_6e35_m00awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00awn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_100/sim/bd_6e35_m00wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00wn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_101/sim/bd_6e35_m00bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00bn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_102/sim/bd_6e35_m00e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m00e_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_103/sim/bd_6e35_m01s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01s2a_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_104/sim/bd_6e35_m01arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01arn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_105/sim/bd_6e35_m01rn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01rn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_106/sim/bd_6e35_m01awn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_107/sim/bd_6e35_m01wn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01wn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_108/sim/bd_6e35_m01bn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01bn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_109/sim/bd_6e35_m01e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m01e_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_110/sim/bd_6e35_m02s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02s2a_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_111/sim/bd_6e35_m02arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02arn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_112/sim/bd_6e35_m02rn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02rn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_113/sim/bd_6e35_m02awn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_114/sim/bd_6e35_m02wn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02wn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_115/sim/bd_6e35_m02bn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m02bn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_116/sim/bd_6e35_m02e_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m02e_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_117/sim/bd_6e35_m03s2a_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m03s2a_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_118/sim/bd_6e35_m03arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m03arn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_119/sim/bd_6e35_m03rn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m03rn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_120/sim/bd_6e35_m03awn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m03awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_121/sim/bd_6e35_m03wn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m03wn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_122/sim/bd_6e35_m03bn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m03bn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_123/sim/bd_6e35_m03e_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m03e_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_124/sim/bd_6e35_m04s2a_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04s2a_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_125/sim/bd_6e35_m04arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04arn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_126/sim/bd_6e35_m04rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_127/sim/bd_6e35_m04awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_128/sim/bd_6e35_m04wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_129/sim/bd_6e35_m04bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_130/sim/bd_6e35_m04e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m04e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_131/sim/bd_6e35_m05s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_132/sim/bd_6e35_m05arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_133/sim/bd_6e35_m05rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_134/sim/bd_6e35_m05awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_135/sim/bd_6e35_m05wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_136/sim/bd_6e35_m05bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_137/sim/bd_6e35_m05e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m05e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_138/sim/bd_6e35_m06s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_139/sim/bd_6e35_m06arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_140/sim/bd_6e35_m06rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_141/sim/bd_6e35_m06awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_142/sim/bd_6e35_m06wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_143/sim/bd_6e35_m06bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_144/sim/bd_6e35_m06e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m06e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_145/sim/bd_6e35_m07s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_146/sim/bd_6e35_m07arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_147/sim/bd_6e35_m07rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_148/sim/bd_6e35_m07awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_149/sim/bd_6e35_m07wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_150/sim/bd_6e35_m07bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_151/sim/bd_6e35_m07e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m07e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_152/sim/bd_6e35_m08s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_153/sim/bd_6e35_m08arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_154/sim/bd_6e35_m08rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_155/sim/bd_6e35_m08awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_156/sim/bd_6e35_m08wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_157/sim/bd_6e35_m08bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_158/sim/bd_6e35_m08e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m08e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_159/sim/bd_6e35_m09s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_160/sim/bd_6e35_m09arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_161/sim/bd_6e35_m09rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_162/sim/bd_6e35_m09awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_163/sim/bd_6e35_m09wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_164/sim/bd_6e35_m09bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_165/sim/bd_6e35_m09e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m09e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_166/sim/bd_6e35_m10s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_167/sim/bd_6e35_m10arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_168/sim/bd_6e35_m10rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_169/sim/bd_6e35_m10awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_170/sim/bd_6e35_m10wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_171/sim/bd_6e35_m10bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_172/sim/bd_6e35_m10e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m10e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_173/sim/bd_6e35_m11s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_174/sim/bd_6e35_m11arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_175/sim/bd_6e35_m11rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_176/sim/bd_6e35_m11awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11awn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_177/sim/bd_6e35_m11wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11wn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_178/sim/bd_6e35_m11bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11bn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_179/sim/bd_6e35_m11e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m11e_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_180/sim/bd_6e35_m12s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_181/sim/bd_6e35_m12arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_182/sim/bd_6e35_m12rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_183/sim/bd_6e35_m12awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_184/sim/bd_6e35_m12wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_185/sim/bd_6e35_m12bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_186/sim/bd_6e35_m12e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m12e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_187/sim/bd_6e35_m13s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_188/sim/bd_6e35_m13arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_189/sim/bd_6e35_m13rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_190/sim/bd_6e35_m13awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_191/sim/bd_6e35_m13wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_192/sim/bd_6e35_m13bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_193/sim/bd_6e35_m13e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m13e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_194/sim/bd_6e35_m14s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_195/sim/bd_6e35_m14arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_196/sim/bd_6e35_m14rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_197/sim/bd_6e35_m14awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_198/sim/bd_6e35_m14wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_199/sim/bd_6e35_m14bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_200/sim/bd_6e35_m14e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m14e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_201/sim/bd_6e35_m15s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_202/sim/bd_6e35_m15arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_203/sim/bd_6e35_m15rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_204/sim/bd_6e35_m15awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_205/sim/bd_6e35_m15wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_206/sim/bd_6e35_m15bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_207/sim/bd_6e35_m15e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m15e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_208/sim/bd_6e35_m16s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_209/sim/bd_6e35_m16arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16arn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_210/sim/bd_6e35_m16rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_211/sim/bd_6e35_m16awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16awn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_212/sim/bd_6e35_m16wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16wn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_213/sim/bd_6e35_m16bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16bn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_214/sim/bd_6e35_m16e_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m16e_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_215/sim/bd_6e35_m17s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17s2a_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_216/sim/bd_6e35_m17arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17arn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_217/sim/bd_6e35_m17rn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17rn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_218/sim/bd_6e35_m17awn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_219/sim/bd_6e35_m17wn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17wn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_220/sim/bd_6e35_m17bn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17bn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_221/sim/bd_6e35_m17e_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m17e_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_222/sim/bd_6e35_m18s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m18s2a_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_223/sim/bd_6e35_m18arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m18arn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_224/sim/bd_6e35_m18rn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_6e35_m18rn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_225/sim/bd_6e35_m18awn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m18awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_226/sim/bd_6e35_m18wn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m18wn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_227/sim/bd_6e35_m18bn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m18bn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_228/sim/bd_6e35_m18e_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m18e_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_229/sim/bd_6e35_m19s2a_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19s2a_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_230/sim/bd_6e35_m19arn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19arn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_231/sim/bd_6e35_m19rn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19rn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_232/sim/bd_6e35_m19awn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19awn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_233/sim/bd_6e35_m19wn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19wn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_234/sim/bd_6e35_m19bn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19bn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_235/sim/bd_6e35_m19e_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m19e_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_236/sim/bd_6e35_m20s2a_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m20s2a_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_237/sim/bd_6e35_m20arn_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_6e35_m20arn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_238/sim/bd_6e35_m20rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m20rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_239/sim/bd_6e35_m20awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m20awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_240/sim/bd_6e35_m20wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m20wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_241/sim/bd_6e35_m20bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m20bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_242/sim/bd_6e35_m20e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m20e_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_243/sim/bd_6e35_m21s2a_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21s2a_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_244/sim/bd_6e35_m21arn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_245/sim/bd_6e35_m21rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_246/sim/bd_6e35_m21awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_247/sim/bd_6e35_m21wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_248/sim/bd_6e35_m21bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_249/sim/bd_6e35_m21e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35_m21e_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/sim/bd_6e35.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_6e35
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INFO: [VRFC 10-311] analyzing module clk_map_imp_51Y3FJ
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INFO: [VRFC 10-311] analyzing module i_nodes_imp_1MS44DT
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1T3ARK4
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1FSNY20
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INFO: [VRFC 10-311] analyzing module m01_exit_pipeline_imp_1YE0YPW
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INFO: [VRFC 10-311] analyzing module m01_nodes_imp_AZWPR2
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INFO: [VRFC 10-311] analyzing module m02_exit_pipeline_imp_1ILMPOK
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INFO: [VRFC 10-311] analyzing module m02_nodes_imp_PGLR45
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INFO: [VRFC 10-311] analyzing module m03_exit_pipeline_imp_1MSDTTW
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INFO: [VRFC 10-311] analyzing module m03_nodes_imp_1J5QS4Z
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INFO: [VRFC 10-311] analyzing module m04_exit_pipeline_imp_1EK7210
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INFO: [VRFC 10-311] analyzing module m04_nodes_imp_1988F8Z
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INFO: [VRFC 10-311] analyzing module m05_exit_pipeline_imp_18OVLJ8
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INFO: [VRFC 10-311] analyzing module m05_nodes_imp_H7UT6T
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INFO: [VRFC 10-311] analyzing module m06_exit_pipeline_imp_16AED1G
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INFO: [VRFC 10-311] analyzing module m06_nodes_imp_IFLAJI
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INFO: [VRFC 10-311] analyzing module m07_exit_pipeline_imp_13QXBNO
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INFO: [VRFC 10-311] analyzing module m07_nodes_imp_1PZ9P7S
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INFO: [VRFC 10-311] analyzing module m08_exit_pipeline_imp_N9M1OK
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INFO: [VRFC 10-311] analyzing module m08_nodes_imp_129ZIN2
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INFO: [VRFC 10-311] analyzing module m09_exit_pipeline_imp_J4QCW4
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INFO: [VRFC 10-311] analyzing module m09_nodes_imp_5TLE20
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_TBR4ZR
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_YEXQU5
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INFO: [VRFC 10-311] analyzing module switchboards_imp_6NOXZD
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/sim/design_a9_1_axi_smc_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_axi_smc_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/sim/design_a9_1_axis_data_fifo_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_axis_data_fifo_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/sim/design_a9_1_axis_data_fifo_1_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_axis_data_fifo_1_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_0/sim/bd_962a_one_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_one_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_2/sim/bd_962a_arsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_arsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_3/sim/bd_962a_rsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_rsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_4/sim/bd_962a_awsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_awsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_5/sim/bd_962a_wsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_wsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_6/sim/bd_962a_bsw_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_bsw_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_7/sim/bd_962a_s00mmu_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s00mmu_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_8/sim/bd_962a_s00tr_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s00tr_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_9/sim/bd_962a_s00sic_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s00sic_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_10/sim/bd_962a_s00a2s_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s00a2s_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_11/sim/bd_962a_sarn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sarn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_12/sim/bd_962a_srn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_srn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_13/sim/bd_962a_s01mmu_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s01mmu_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_14/sim/bd_962a_s01tr_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s01tr_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_15/sim/bd_962a_s01sic_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s01sic_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_16/sim/bd_962a_s01a2s_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s01a2s_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_17/sim/bd_962a_sawn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sawn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_18/sim/bd_962a_swn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_swn_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_19/sim/bd_962a_sbn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sbn_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_20/sim/bd_962a_s02mmu_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s02mmu_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_21/sim/bd_962a_s02tr_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s02tr_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_22/sim/bd_962a_s02sic_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s02sic_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_23/sim/bd_962a_s02a2s_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s02a2s_0
|
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_24/sim/bd_962a_sawn_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sawn_1
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_25/sim/bd_962a_swn_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_swn_1
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_26/sim/bd_962a_sbn_1.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sbn_1
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_27/sim/bd_962a_s03mmu_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_s03mmu_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_28/sim/bd_962a_s03tr_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_962a_s03tr_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_29/sim/bd_962a_s03sic_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_962a_s03sic_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_30/sim/bd_962a_s03a2s_0.sv" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module bd_962a_s03a2s_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_31/sim/bd_962a_sawn_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sawn_2
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_32/sim/bd_962a_swn_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_swn_2
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_33/sim/bd_962a_sbn_2.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_sbn_2
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_34/sim/bd_962a_m00s2a_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_m00s2a_0
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_35/sim/bd_962a_m00arn_0.sv" into library xil_defaultlib
|
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INFO: [VRFC 10-311] analyzing module bd_962a_m00arn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_36/sim/bd_962a_m00rn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_m00rn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_37/sim/bd_962a_m00awn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_m00awn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_38/sim/bd_962a_m00wn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_m00wn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_39/sim/bd_962a_m00bn_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_m00bn_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_40/sim/bd_962a_m00e_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a_m00e_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:2214]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/sim/design_a9_1_CHANN_EN_1.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_CHANN_EN_1'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/sim/design_a9_1_CHANN_EN_2.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_CHANN_EN_2'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/sim/design_a9_1_STIM_SPI_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_STIM_SPI_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/sim/design_a9_1_ZCHECK_SPI_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_ZCHECK_SPI_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/sim/design_a9_1_axi_dma_2_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_dma_2_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/sim/design_a9_1_axi_dma_1_1.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_dma_1_1'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/sim/design_a9_1_axi_bram_ctrl_0_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_0_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/sim/design_a9_1_axi_bram_ctrl_1_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_1_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/sim/design_a9_1_axi_bram_ctrl_2_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_2_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/sim/design_a9_1_axi_bram_ctrl_3_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_3_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/sim/design_a9_1_axi_bram_ctrl_4_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_4_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/sim/design_a9_1_axi_dma_0_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_dma_0_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/sim/design_a9_1_axi_dma_1_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_dma_1_0'
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|
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/sim/design_a9_1_axi_gpio_0_0.vhd" into library xil_defaultlib
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|
INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_gpio_0_0'
|
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/sim/bd_6e35_psr_aclk_0.vhd" into library xil_defaultlib
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|
INFO: [VRFC 10-3107] analyzing entity 'bd_6e35_psr_aclk_0'
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|
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/sim/design_a9_1_rst_ps7_0_50M_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_rst_ps7_0_50M_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/sim/bd_962a_psr_aclk_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'bd_962a_psr_aclk_0'
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|
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/sim/design_a9_1_axi_gpio_1_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_gpio_1_0'
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/sim/design_a9_1_CHANN_EN_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_CHANN_EN_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/sim/design_a9_1_CHANN_SEL_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_CHANN_SEL_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/sim/design_a9_1_axi_quad_spi_0_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_quad_spi_0_0'
|
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/sim/design_a9_1_axi_bram_ctrl_3_1.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_3_1'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_Z_IO_0/sim/design_a9_1_Z_IO_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_Z_IO_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/sim/design_a9_1_axi_bram_ctrl_5_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_5_0'
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/sim/design_a9_1_axi_bram_ctrl_6_0.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'design_a9_1_axi_bram_ctrl_6_0'
|
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
|
|
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
|
|
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
|
|
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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|
INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
|
|
INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
|
|
WARNING: [VRFC 10-3607] overwriting existing primary unit 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl:2826]
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|
run_program: Time (s): cpu = 00:00:10 ; elapsed = 00:00:58 . Memory (MB): peak = 5361.887 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '58' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
|
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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|
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
|
|
Starting static elaboration
|
|
Pass Through NonSizing Optimizer
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|
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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|
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
|
|
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
|
|
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
|
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
|
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
|
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
|
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
|
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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|
WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
|
|
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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|
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
|
|
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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|
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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|
Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
|
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
|
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
|
|
Compiling module xil_defaultlib.ads1299_if
|
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
|
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
|
|
Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
|
|
Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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|
Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
|
|
Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
|
|
Compiling module unisims_ver.GND
|
|
Compiling module unisims_ver.FDRE_default
|
|
Compiling module unisims_ver.CARRY4
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|
Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 5361.887 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '26' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 5361.887 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:01:09 ; elapsed = 00:02:15 . Memory (MB): peak = 5361.887 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/clk}} {{/pl_top_tb/DUT/u_eeg_emg_upload/rst_n}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/diff_pkt_data_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/emg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/stop_sample}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_data_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_fifo_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en_dly}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_en_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_data}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/msg_crc}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16_out}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc_vld}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 1 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 5361.887 ; gain = 0.000
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
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add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
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add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
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add_wave -into {hw_ila_data_1.wcfg} -radix hex { {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/crc16} {u_pl_top/u_eeg_emg_upload/crc16_out} {u_pl_top/u_eeg_emg_upload/crc_vld} {u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast} {u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid} {u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num} {u_pl_top/u_eeg_emg_upload/emg_send_package_num} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en} {u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly} {u_pl_top/u_eeg_emg_upload/fifo_rd_data} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid} {u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid} }
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close_hw_manager
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open_hw_manager
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connect_hw_server -allow_non_jtag
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
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INFO: [Labtools 27-3417] Launching cs_server...
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INFO: [Labtools 27-2221] Launch Output:
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******** Xilinx cs_server v2023.1.0
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****** Build date : Apr 10 2023-23:59:24
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**** Build number : 2023.1.1681142364
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** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
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open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
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set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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current_hw_device [get_hw_devices xc7z020_1]
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refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 16:50:29
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 16:50:29
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 5459.062 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 16:53:39
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 16:53:39
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 5459.062 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq8'hXX [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 16:54:03
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 16:54:03
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 5459.062 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'b0 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b0 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq8'hXX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq8'hA5 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-01 16:55:27
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-01 16:55:27
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 6033.758 ; gain = 0.000
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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reset_run synth_1
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WARNING: [Vivado 12-1017] Problems encountered:
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1. Failed to delete one or more files in run directory D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1
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launch_runs synth_1 -jobs 20
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[Wed Sep 2 09:34:14 2026] Launched synth_1...
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Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
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close_design
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open_run synth_1 -name synth_1
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Design is defaulting to impl run constrset: constrs_1
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Design is defaulting to synth run part: xc7z020clg400-2
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.dcp' for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp' for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32.dcp' for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.dcp' for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6033.758 ; gain = 0.000
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INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Chipscope 16-324] Core: u_pl_top/u_cur_mon_top/u_vio_cur_flt_state UUID: 8a67dbc2-bda6-5e4b-b982-bb6511a2b4be
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:61]
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|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
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|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc:50]
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v4/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
INFO: [Project 1-1714] 477 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 6033.758 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 188 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 27 instances
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 3 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 144 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 14 instances
|
|
|
|
open_run: Time (s): cpu = 00:00:46 ; elapsed = 00:00:35 . Memory (MB): peak = 6033.758 ; gain = 0.000
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_rst ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list mux_pwr_en_OBUF ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/stop_sample ]]
|
|
reset_run synth_1
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1
|
|
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
|
|
[Wed Sep 2 09:42:57 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/synth_1/runme.log
|
|
[Wed Sep 2 09:42:57 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/runme.log
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
INFO: [Project 1-1918] Creating Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa ...
|
|
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
|
|
INFO: [Project 1-1941] Successfully created Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v4/c64pro_top.xsa
|
|
save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
|
|
close_sim
|
|
INFO: xsimkernel Simulation Memory Usage: 31252 KB (Peak: 31252 KB), Simulation CPU Usage: 13437 ms
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
exit
|
|
INFO: [Common 17-206] Exiting Vivado at Wed Sep 2 11:20:24 2026...
|