273 lines
7.9 KiB
Verilog
273 lines
7.9 KiB
Verilog
`timescale 1 ns / 1 ps
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module eeg_top1#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CHIPSET_QTY = 4 ,//8
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parameter CHIPSET_CH_QTY = 8 ,
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parameter SPIS_QTY = 2 ,//4
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parameter SPI_SLAVE_QTY = 2 ,
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parameter SPI_CLK_DIV = 3 ,
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parameter SPI_DATA_WIDTH = 8 ,
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parameter SPI_TRANS_PERIOD = 2000 //Unit: ns
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output interrupt ,
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output [32-1:0] axis_record_tdata ,
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output axis_record_tlast ,
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input axis_record_tready ,
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output axis_record_tvalid ,
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output [CHIPSET_QTY-1:0] cs ,
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output [ SPIS_QTY-1:0] sclk ,
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output [ SPIS_QTY-1:0] mosi ,
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input [ SPIS_QTY-1:0] miso ,
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input [ SPIS_QTY-1:0] drdy ,
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output [ SPIS_QTY-1:0] start ,
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output [ 4-1:0] debug_sig
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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wire [32-1:0] eeg_er ;
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wire [32-1:0] eeg_cr ;
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wire [32-1:0] eeg_sr ;
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wire [32*SPIS_QTY-1:0] eeg_tr_array ;
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wire [32*SPIS_QTY-1:0] eeg_rr_array ;
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wire eeg_sr_r_evt ;
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wire [SPI_SLAVE_QTY-1:0] cs_w[SPIS_QTY-1:0] ;
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wire send_enable[SPIS_QTY-1:0] ;
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wire [ 8-1:0] send_cs_n[SPIS_QTY-1:0] ;
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wire [ 8-1:0] send_length[SPIS_QTY-1:0] ;
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wire [32-1:0] send_data_array[SPIS_QTY-1:0] ;
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wire [32-1:0] recv_data_array[SPIS_QTY-1:0] ;
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wire recv_data_en_array[SPIS_QTY-1:0];
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wire [ 8-1:0] t_cs_n[SPIS_QTY-1:0] ;
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wire [ 8-1:0] t_tdata[SPIS_QTY-1:0] ;
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wire t_tlast[SPIS_QTY-1:0] ;
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wire t_tready[SPIS_QTY-1:0] ;
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wire t_tvalid[SPIS_QTY-1:0] ;
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wire [ 8-1:0] r_tdata[SPIS_QTY-1:0] ;
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wire r_tlast[SPIS_QTY-1:0] ;
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wire r_tvalid[SPIS_QTY-1:0] ;
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wire cnv_start[SPIS_QTY-1:0] ;
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wire cnv_drdy[SPIS_QTY-1:0] ;
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wire upload_round[SPIS_QTY-1:0] ;
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//------------------------------------------ record stream rx
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wire [32-1:0] cnv_res_tdata[SPIS_QTY-1:0] ;
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wire cnv_res_tlast[SPIS_QTY-1:0] ;
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wire cnv_res_tready[SPIS_QTY-1:0] ;
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wire cnv_res_tvalid[SPIS_QTY-1:0] ;
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wire [32*SPIS_QTY-1:0] cnv_res_tdata_array ;
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wire [ SPIS_QTY-1:0] cnv_res_tlast_array ;
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wire [ SPIS_QTY-1:0] cnv_res_tready_array ;
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wire [ SPIS_QTY-1:0] cnv_res_tvalid_array ;
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wire record_enable ;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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eeg_config#
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(
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.SPIS_QTY ( 2 ),//4
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.SPI_DATA_WIDTH ( 8 )
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)
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u_eeg_config
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_addr ),
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.bram_clk ( bram_clk ),
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.bram_din ( bram_din ),
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.bram_dout ( bram_dout ),
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.bram_en ( bram_en ),
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.bram_rst ( bram_rst ),
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.bram_we ( bram_we ),
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//eeg
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.eeg_er ( eeg_er ),
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.eeg_cr ( eeg_cr ),
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.eeg_sr ( eeg_sr ),
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.eeg_tr_array ( eeg_tr_array ),
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.eeg_rr_array ( eeg_rr_array ),
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.eeg_sr_r_evt ( eeg_sr_r_evt )
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);
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generate
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for(i=0;i<SPIS_QTY;i=i+1) begin : transmit_arrange
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ads1299_arrange#
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(
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.CLK_PERIOD ( 10 ),
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.SPI_DATA_WIDTH ( 8 ),
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.SPI_TRANS_PERIOD ( SPI_TRANS_PERIOD )
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)
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u_ads1299_arrange
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.send_cs_n ( send_cs_n[i] ),
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.send_enable ( send_enable[i] ),
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.send_length ( send_length[i] ),
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.send_data_array ( send_data_array[i] ),
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.recv_data_en ( recv_data_en_array[i] ),
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.recv_data_array ( recv_data_array[i] ),
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.t_cs_n ( t_cs_n[i] ),
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.t_tdata ( t_tdata[i] ),
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.t_tlast ( t_tlast[i] ),
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.t_tready ( t_tready[i] ),
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.t_tvalid ( t_tvalid[i] ),
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.r_tdata ( r_tdata[i] ),
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.r_tlast ( r_tlast[i] ),
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.r_tvalid ( r_tvalid[i] ),
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.rdatac_enable ( record_enable ),
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.cnv_start ( cnv_start[i] ),
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.cnv_drdy ( cnv_drdy[0] ),
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.upload_round ( upload_round[i] )
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);
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end
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endgenerate
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generate
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for(i=0;i<SPIS_QTY;i=i+1) begin : trans_if
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ads1299_if1#
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(
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.SPI_CLK_DIV ( SPI_CLK_DIV ),
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.SPI_DATA_WIDTH ( SPI_DATA_WIDTH ),
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.SPI_SLAVE_QTY ( SPI_SLAVE_QTY )
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)
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u_ads1299_if1
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.upload_enable ( record_enable ),
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.upload_round ( upload_round[i] ),
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//------------------------------------------ spi direct communication
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.t_cs_n ( t_cs_n[i] ),
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.t_tdata ( t_tdata[i] ),
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.t_tlast ( t_tlast[i] ),
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.t_tready ( t_tready[i] ),
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.t_tvalid ( t_tvalid[i] ),
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.r_tdata ( r_tdata[i] ),
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.r_tlast ( r_tlast[i] ),
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.r_tvalid ( r_tvalid[i] ),
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//------------------------------------------ record stream rx
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.cnv_res_tdata ( cnv_res_tdata[i] ),
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.cnv_res_tlast ( cnv_res_tlast[i] ),
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.cnv_res_tready ( cnv_res_tready[i] ),
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.cnv_res_tvalid ( cnv_res_tvalid[i] ),
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//------------------------------------------ device spi
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.cs ( cs_w[i] ),
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.sclk ( sclk[i] ),
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.mosi ( mosi[i] ),
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.miso ( miso[i] )
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);
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end
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endgenerate
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eeg_upload#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.CHIPSET_QTY ( SPIS_QTY ),
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.CH_OF_CHIPSET ( CHIPSET_CH_QTY*SPI_SLAVE_QTY )
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)
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u_eeg_upload
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trans_round ( upload_round[0] ),
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.cnv_res_tdata_array ( cnv_res_tdata_array ),
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.cnv_res_tlast_array ( cnv_res_tlast_array ),
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.cnv_res_tready_array ( cnv_res_tready_array ),
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.cnv_res_tvalid_array ( cnv_res_tvalid_array ),
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.axi_str_rxd_tdata ( axis_record_tdata ),
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.axi_str_rxd_tlast ( axis_record_tlast ),
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.axi_str_rxd_tready ( axis_record_tready ),
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.axi_str_rxd_tvalid ( axis_record_tvalid )
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);
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign record_enable = eeg_cr[31];
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assign start = {cnv_start[0],cnv_start[0]};
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generate
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for(i=0;i<SPIS_QTY;i=i+1) begin : mapping
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assign send_enable[i] = eeg_er[i];
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assign send_cs_n[i] = {6'd0, eeg_cr[5*i+1:5*i+0]};//[4*i+1:4*i+0]
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assign send_length[i] = {5'd0, eeg_cr[5*i+4:5*i+2]};//[4*i+3:4*i+2]
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assign send_data_array[i] = eeg_tr_array[32*i+31:32*i];
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assign eeg_rr_array[32*i+31:32*i] = recv_data_array[i];
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assign cs[SPI_SLAVE_QTY*(i+1)-1 : SPI_SLAVE_QTY*i] = cs_w[i];
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assign cnv_drdy[i] = drdy[i];
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assign cnv_res_tdata_array[32*i+31 : 32*i] = cnv_res_tdata[i];
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assign cnv_res_tlast_array[i] = cnv_res_tlast[i];
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assign cnv_res_tvalid_array[i] = cnv_res_tvalid[i];
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assign cnv_res_tready[i] = cnv_res_tready_array[i];
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end
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endgenerate
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assign interrupt = 1'b0;
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assign debug_sig[0] = record_enable;
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assign debug_sig[1] = 1'b0;
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assign debug_sig[2] = 1'b0;
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assign debug_sig[3] = 1'b0;
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endmodule
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