155 lines
3.3 KiB
Verilog
155 lines
3.3 KiB
Verilog
`timescale 1ns/1ps
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module ads1299_mod#
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(
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parameter DATA_WIDTH = 8 ,
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parameter WIRE_DELAY = 11
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)
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(
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input cs ,
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input sclk ,
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input mosi ,
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output miso ,
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output reg drdy ,
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input start
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam T_CLK = 31250 ; //ns
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localparam RDATAC = 8'h08 ;
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localparam SDATAC = 8'h11 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [ 8 - 1:0] serial_in ;
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reg [ 8 - 1:0] rx_cnt ;
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reg [ 8 - 1:0] rx_data ;
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reg [ 8 - 1:0] tx_cnt ;
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reg [ 8 - 1:0] reg_data ;
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reg [ 8 - 1:0] cnv_data ;
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reg [ 8 - 1:0] start_t_cnt ;
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reg cnv_en ;
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reg [ 8 - 1:0] r_cnt ;
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 1;
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while(1) begin
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@ ( posedge cnv_en );
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while ( cnv_en ) begin
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@ ( posedge clk );
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drdy <= cnv_en? 1'b0:1'b1;
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@ ( negedge sclk );
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drdy <= 1'b1;
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end
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end
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end
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initial begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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drdy <= 1'b1;
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end
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//RX
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always @ ( negedge sclk or negedge rst_n or posedge cs ) begin
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if( !rst_n || cs )
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rx_cnt <= 0;
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else if ( rx_cnt != DATA_WIDTH )
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rx_cnt <= rx_cnt + 1'b1;
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else
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rx_cnt <= 1;
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end
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always @ ( negedge sclk or negedge rst_n or negedge cs ) begin
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if( !rst_n || cs )
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serial_in <= 0;
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else
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serial_in <= {serial_in[6:0], mosi};
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end
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always @ ( rx_cnt ) begin
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if( rx_cnt == 8 )
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rx_data <= serial_in;
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end
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//data
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always@( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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start_t_cnt <= 0;
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else if ( start ) begin
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if ( start_t_cnt != 3 )
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start_t_cnt <= start_t_cnt + 1'b1;
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end else
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start_t_cnt <= 0;
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end
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always@( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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cnv_en <= 1'b0;
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else if ( start_t_cnt == 3 )
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cnv_en <= 1'b1;
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else
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cnv_en <= 1'b0;
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end
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always@( posedge sclk or negedge rst_n or posedge cs ) begin
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if ( !rst_n )
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r_cnt <= 0;
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else if ( cs )
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r_cnt <= 0;
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else
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r_cnt <= r_cnt + 1'b1;
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end
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always@( posedge sclk or negedge rst_n ) begin
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if ( !rst_n ) begin
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cnv_data <= 0;
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end else if ( cnv_en && r_cnt[2:0] == 3'd0 && !cs ) begin
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cnv_data <= cnv_data + 1'b1;
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end
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end
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always @ ( negedge cs or negedge rst_n or tx_cnt ) begin
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if ( !rst_n )
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reg_data <= 8'h55;
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else if ( tx_cnt == 7 )
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reg_data <= reg_data + 1'b1;
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end
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//TX
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always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
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if( !rst_n || cs )
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tx_cnt <= DATA_WIDTH;
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else if ( tx_cnt != 0 )
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tx_cnt <= tx_cnt - 1'b1;
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else
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tx_cnt <= DATA_WIDTH-1;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign #17 miso = (tx_cnt == DATA_WIDTH)? 1'b0:( cnv_en? cnv_data[tx_cnt]:reg_data[tx_cnt] );
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endmodule
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