173 lines
4.7 KiB
Verilog
173 lines
4.7 KiB
Verilog
`timescale 1 ns / 1 ps
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module accel_top#
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(
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parameter CLK_PERIOD = 10
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output interrupt ,
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output [16*3-1:0] accel_data ,
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output accel_spi_cs ,
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output accel_spi_sclk ,
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output accel_spi_mosi ,
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input accel_spi_miso ,
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input accel_int0 ,
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input accel_int1
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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// wire stream_enable ;
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// wire [ 8-1:0] t_tdata ;
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// wire t_tready ;
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// wire t_tvalid ;
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// wire [ 8-1:0] t_tdata_ps ;
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// wire t_tready_ps ;
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// wire t_tvalid_ps ;
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// wire [ 8-1:0] t_tdata_pl ;
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// wire t_tready_pl ;
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// wire t_tvalid_pl ;
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// wire [ 8-1:0] r_tdata ;
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// wire r_tvalid ;
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// wire [ 8-1:0] r_tdata_ps ;
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// wire r_tvalid_ps ;
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// wire [ 8-1:0] r_tdata_pl ;
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// wire r_tvalid_pl ;
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// wire [16-1:0] out_x ;
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// wire [16-1:0] out_y ;
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// wire [16-1:0] out_z ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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// accel_config#
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// (
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// .SPI_DATA_WIDTH ( 8 )
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// )
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// u_accel_config
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// (
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// .clk ( clk ),
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// .rst_n ( rst_n ),
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// .bram_addr ( bram_addr ),
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// .bram_clk ( bram_clk ),
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// .bram_din ( bram_din ),
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// .bram_dout ( bram_dout ),
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// .bram_en ( bram_en ),
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// .bram_rst ( bram_rst ),
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// .bram_we ( bram_we ),
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// .t_tdata ( t_tdata_ps ),
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// .t_tready ( t_tready_ps ),
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// .t_tvalid ( t_tvalid_ps ),
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// .r_tdata ( r_tdata_ps ),
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// .r_tvalid ( r_tvalid_ps ),
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// .stream_enable ( stream_enable )
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// );
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// accel_stream#
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// (
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// .CLK_PERIOD ( 10 ),
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// .SPI_DATA_WIDTH ( 8 )
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// )
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// u_accel_stream
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// (
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// .clk ( clk ),
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// .rst_n ( rst_n ),
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// .enable ( stream_enable ),
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// .accel_int ( accel_int0 ),
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// .t_tdata ( t_tdata_ps ),
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// .t_tready ( t_tready_ps ),
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// .t_tvalid ( t_tvalid_ps ),
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// .r_tdata ( r_tdata_ps ),
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// .r_tvalid ( r_tvalid_ps ),
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// .out_x ( out_x ),
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// .out_y ( out_y ),
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// .out_z ( out_z )
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// );
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// lis2dw12_spi#
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// (
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// .CLK_PERIOD ( 10 ),
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// .CLK_DIV ( 10 ),
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// .DATA_WIDTH ( 8 )
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// )
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// u_lis2dw12_spi
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// (
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// .clk ( clk ),
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// .rst_n ( rst_n ),
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// .t_tdata ( t_tdata ),
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// .t_tready ( t_tready ),
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// .t_tvalid ( t_tvalid ),
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// .r_tdata ( r_tdata ),
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// .r_tvalid ( r_tvalid ),
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// .cs ( cs ),
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// .sclk ( sclk ),
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// .mosi ( mosi ),
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// .miso ( miso )
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// );
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//*****************************************************************************
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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// assign t_tdata = ( stream_enable)? t_tdata_pl :t_tdata_ps;
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// assign t_tvalid = ( stream_enable)? t_tvalid_pl:t_tvalid_ps;
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// assign t_tready_ps = (~stream_enable)? t_tready:0;
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// assign t_tready_pl = ( stream_enable)? t_tready:0;
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// assign r_tdata_ps = (~stream_enable)? r_tdata :0;
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// assign r_tvalid_ps = (~stream_enable)? r_tvalid:0;
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// assign r_tdata_pl = ( stream_enable)? r_tdata :0;
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// assign r_tvalid_pl = ( stream_enable)? r_tvalid:0;
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// assign accel_data[15: 0] = out_x;
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// assign accel_data[31:16] = out_y;
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// assign accel_data[47:32] = out_z;
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assign bram_dout = 0;
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assign interrupt = 1'b0;
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assign accel_data = 0;
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assign accel_spi_cs = 1'b0;
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assign accel_spi_sclk = 1'b0;
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assign accel_spi_mosi = 1'b0;
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endmodule
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