478 lines
40 KiB
Tcl
478 lines
40 KiB
Tcl
#____________________________________________________________________________ad7689
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set_property VCCAUX_IO DONTCARE [get_ports ad7689_cnv]
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set_property IOSTANDARD LVCMOS33 [get_ports ad7689_cnv]
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set_property PACKAGE_PIN C20 [get_ports ad7689_cnv]
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set_property VCCAUX_IO DONTCARE [get_ports ad7689_spi_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports ad7689_spi_sclk]
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set_property PACKAGE_PIN E19 [get_ports ad7689_spi_sclk]
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set_property VCCAUX_IO DONTCARE [get_ports ad7689_spi_mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports ad7689_spi_mosi]
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set_property PACKAGE_PIN D20 [get_ports ad7689_spi_mosi]
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set_property VCCAUX_IO DONTCARE [get_ports ad7689_spi_miso]
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set_property IOSTANDARD LVCMOS33 [get_ports ad7689_spi_miso]
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set_property PACKAGE_PIN F20 [get_ports ad7689_spi_miso]
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#____________________________________________________________________________zcheck
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set_property VCCAUX_IO DONTCARE [get_ports rst_ad5941]
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set_property IOSTANDARD LVCMOS33 [get_ports rst_ad5941]
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set_property PACKAGE_PIN R19 [get_ports rst_ad5941]
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set_property VCCAUX_IO DONTCARE [get_ports zcheck_spi_cs]
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set_property IOSTANDARD LVCMOS33 [get_ports zcheck_spi_cs]
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set_property PACKAGE_PIN P19 [get_ports zcheck_spi_cs]
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set_property VCCAUX_IO DONTCARE [get_ports zcheck_spi_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports zcheck_spi_sclk]
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set_property PACKAGE_PIN P18 [get_ports zcheck_spi_sclk]
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set_property VCCAUX_IO DONTCARE [get_ports zcheck_spi_mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports zcheck_spi_mosi]
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set_property PACKAGE_PIN N18 [get_ports zcheck_spi_mosi]
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set_property VCCAUX_IO DONTCARE [get_ports zcheck_spi_miso]
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set_property IOSTANDARD LVCMOS33 [get_ports zcheck_spi_miso]
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set_property PACKAGE_PIN R18 [get_ports zcheck_spi_miso]
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set_property VCCAUX_IO DONTCARE [get_ports z_io]
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set_property IOSTANDARD LVCMOS33 [get_ports z_io]
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set_property PACKAGE_PIN G19 [get_ports z_io]
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#set_property VCCAUX_IO DONTCARE [get_ports {z_io[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {z_io[1]}]
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#set_property PACKAGE_PIN F17 [get_ports {z_io[1]}]
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#set_property VCCAUX_IO DONTCARE [get_ports {z_io[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {z_io[2]}]
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#set_property PACKAGE_PIN H16 [get_ports {z_io[2]}]
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#____________________________________________________________________________other
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set_property VCCAUX_IO DONTCARE [get_ports pudc]
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set_property IOSTANDARD LVCMOS33 [get_ports pudc]
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set_property PACKAGE_PIN U13 [get_ports pudc]
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set_property VCCAUX_IO DONTCARE [get_ports stim_pwr_en]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_pwr_en]
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set_property PACKAGE_PIN F19 [get_ports stim_pwr_en]
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set_property VCCAUX_IO DONTCARE [get_ports ref_sw_en]
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set_property IOSTANDARD LVCMOS33 [get_ports ref_sw_en]
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set_property PACKAGE_PIN A20 [get_ports ref_sw_en]
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set_property VCCAUX_IO DONTCARE [get_ports ref_sw]
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set_property IOSTANDARD LVCMOS33 [get_ports ref_sw]
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set_property PACKAGE_PIN B20 [get_ports ref_sw]
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#____________________________________________________________________________ELEC_MUX_IN
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set_property VCCAUX_IO DONTCARE [get_ports {elec_mux_in[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {elec_mux_in[0]}]
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set_property PACKAGE_PIN R17 [get_ports {elec_mux_in[0]}]
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set_property VCCAUX_IO DONTCARE [get_ports {elec_mux_in[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {elec_mux_in[1]}]
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set_property PACKAGE_PIN R16 [get_ports {elec_mux_in[1]}]
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set_property VCCAUX_IO DONTCARE [get_ports {elec_mux_in[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {elec_mux_in[2]}]
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set_property PACKAGE_PIN R14 [get_ports {elec_mux_in[2]}]
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set_property VCCAUX_IO DONTCARE [get_ports {elec_mux_in[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {elec_mux_in[3]}]
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set_property PACKAGE_PIN T16 [get_ports {elec_mux_in[3]}]
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#____________________________________________________________________________CHANN_EN
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set_property VCCAUX_IO DONTCARE [get_ports {chann_en[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_en[0]}]
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set_property PACKAGE_PIN W18 [get_ports {chann_en[0]}]
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set_property VCCAUX_IO DONTCARE [get_ports {chann_en[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_en[1]}]
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set_property PACKAGE_PIN U20 [get_ports {chann_en[1]}]
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#set_property VCCAUX_IO DONTCARE [get_ports {chann_en[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {chann_en[2]}]
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#set_property PACKAGE_PIN V10 [get_ports {chann_en[2]}]
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#set_property VCCAUX_IO DONTCARE [get_ports {chann_en[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {chann_en[3]}]
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#set_property PACKAGE_PIN W10 [get_ports {chann_en[3]}]
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set_property VCCAUX_IO DONTCARE [get_ports {chann_sel[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_sel[0]}]
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set_property PACKAGE_PIN V20 [get_ports {chann_sel[0]}]
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set_property VCCAUX_IO DONTCARE [get_ports {chann_sel[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_sel[1]}]
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set_property PACKAGE_PIN V18 [get_ports {chann_sel[1]}]
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set_property VCCAUX_IO DONTCARE [get_ports {chann_sel[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_sel[2]}]
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set_property PACKAGE_PIN W19 [get_ports {chann_sel[2]}]
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set_property VCCAUX_IO DONTCARE [get_ports {chann_sel[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {chann_sel[3]}]
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set_property PACKAGE_PIN W20 [get_ports {chann_sel[3]}]
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#____________________________________________________________________________CHANN_EN
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set_property VCCAUX_IO DONTCARE [get_ports rec_pwr_en]
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set_property IOSTANDARD LVCMOS33 [get_ports rec_pwr_en]
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set_property PACKAGE_PIN G20 [get_ports rec_pwr_en]
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set_property VCCAUX_IO DONTCARE [get_ports mux_pwr_en]
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set_property IOSTANDARD LVCMOS33 [get_ports mux_pwr_en]
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set_property PACKAGE_PIN P16 [get_ports mux_pwr_en]
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#____________________________________________________________________________display led¡¢
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set_property VCCAUX_IO DONTCARE [get_ports led_rsv]
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set_property IOSTANDARD LVCMOS33 [get_ports led_rsv]
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set_property PACKAGE_PIN W15 [get_ports led_rsv]
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set_property VCCAUX_IO DONTCARE [get_ports led_usb]
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set_property IOSTANDARD LVCMOS33 [get_ports led_usb]
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set_property PACKAGE_PIN Y18 [get_ports led_usb]
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set_property VCCAUX_IO DONTCARE [get_ports led_state]
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set_property IOSTANDARD LVCMOS33 [get_ports led_state]
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set_property PACKAGE_PIN Y19 [get_ports led_state]
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set_property VCCAUX_IO DONTCARE [get_ports led_stim]
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set_property IOSTANDARD LVCMOS33 [get_ports led_stim]
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set_property PACKAGE_PIN F16 [get_ports led_stim]
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#____________________________________________________________________________STIM
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set_property VCCAUX_IO DONTCARE [get_ports stim_spi_cs]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_spi_cs]
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set_property PACKAGE_PIN Y8 [get_ports stim_spi_cs]
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set_property VCCAUX_IO DONTCARE [get_ports stim_spi_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_spi_sclk]
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set_property PACKAGE_PIN W9 [get_ports stim_spi_sclk]
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set_property VCCAUX_IO DONTCARE [get_ports stim_spi_mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_spi_mosi]
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set_property PACKAGE_PIN W11 [get_ports stim_spi_mosi]
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set_property VCCAUX_IO DONTCARE [get_ports stim_spi_miso]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_spi_miso]
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set_property PACKAGE_PIN W8 [get_ports stim_spi_miso]
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set_property VCCAUX_IO DONTCARE [get_ports stim_clk400k]
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set_property IOSTANDARD LVCMOS33 [get_ports stim_clk400k]
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set_property PACKAGE_PIN Y9 [get_ports stim_clk400k]
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set_property VCCAUX_IO DONTCARE [get_ports {gpio[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {gpio[0]}]
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set_property PACKAGE_PIN Y11 [get_ports {gpio[0]}]
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set_property VCCAUX_IO DONTCARE [get_ports {gpio[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {gpio[1]}]
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set_property PACKAGE_PIN Y12 [get_ports {gpio[1]}]
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set_property VCCAUX_IO DONTCARE [get_ports {gpio[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {gpio[2]}]
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set_property PACKAGE_PIN Y13 [get_ports {gpio[2]}]
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 32 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 32 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 2 [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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set_property port_width 16 [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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set_property port_width 16 [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property port_width 8 [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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set_property port_width 16 [get_debug_ports u_ila_0/probe7]
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connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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set_property port_width 16 [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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set_property port_width 2 [get_debug_ports u_ila_0/probe9]
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connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]}]]
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create_debug_port u_ila_0 probe
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
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set_property port_width 9 [get_debug_ports u_ila_0/probe10]
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connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]}]]
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create_debug_port u_ila_0 probe
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
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set_property port_width 8 [get_debug_ports u_ila_0/probe11]
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connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]}]]
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create_debug_port u_ila_0 probe
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
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connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]}]]
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create_debug_port u_ila_0 probe
|
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
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set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
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connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
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set_property port_width 16 [get_debug_ports u_ila_0/probe16]
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|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
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set_property port_width 9 [get_debug_ports u_ila_0/probe17]
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|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
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set_property port_width 16 [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
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set_property port_width 13 [get_debug_ports u_ila_0/probe23]
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connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
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set_property port_width 4 [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
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set_property port_width 32 [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]}]]
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
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set_property port_width 8 [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]}]]
|
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
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set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]}]]
|
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create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]}]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axis_eeg24_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axis_eeg24_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_emg_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/axis_emg_tlast_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_stim_config/bram_en]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/emg_ads1299_spi_cs]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/emg_ads1299_spi_miso]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/emg_ads1299_spi_mosi]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/emg_ads1299_spi_sclk]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/emg_ads1299_spi_sclk_tmp]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_rst]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/in004_out]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/m_axis_eeg_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_eeg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_emg_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list u_pl_top/m_axis_emg_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
|
connect_debug_port u_ila_0/probe65 [get_nets [list u_pl_top/m_axis_record_tfull]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
|
connect_debug_port u_ila_0/probe66 [get_nets [list u_pl_top/m_axis_record_tlast]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
|
connect_debug_port u_ila_0/probe67 [get_nets [list u_pl_top/m_axis_record_tready]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
|
|
connect_debug_port u_ila_0/probe68 [get_nets [list u_pl_top/m_axis_record_tvalid]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
|
|
connect_debug_port u_ila_0/probe69 [get_nets [list mux_pwr_en_OBUF]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
|
|
connect_debug_port u_ila_0/probe70 [get_nets [list u_pl_top/stop_sample]]
|
|
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
|
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
|
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
|
connect_debug_port dbg_hub/clk [get_nets clk]
|