31 lines
1.2 KiB
Batchfile
31 lines
1.2 KiB
Batchfile
@echo off
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REM ****************************************************************************
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REM Vivado (TM) v2023.1 (64-bit)
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REM
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REM Filename : compile.bat
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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for compiling the simulation design source files
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REM
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REM Generated by Vivado on Thu Sep 03 09:56:46 +0800 2026
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REM SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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REM
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REM IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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REM
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REM usage: compile.bat
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REM
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REM ****************************************************************************
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REM compile Verilog/System Verilog design sources
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echo "xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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call xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj -log xvlog.log
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call type xvlog.log > compile.log
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REM compile VHDL design sources
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echo "xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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call xvhdl --incr --relax -prj pl_top_tb_vhdl.prj -log xvhdl.log
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call type xvhdl.log >> compile.log
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if "%errorlevel%"=="1" goto END
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if "%errorlevel%"=="0" goto SUCCESS
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:END
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exit 1
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:SUCCESS
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exit 0
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