276 lines
14 KiB
Plaintext
276 lines
14 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Fri Sep 4 15:37:38 2026
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| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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| Command : report_utilization -file c64pro_top_utilization_placed.rpt -pb c64pro_top_utilization_placed.pb
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| Design : c64pro_top
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| Device : xc7z020clg400-2
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| Speed File : -2
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| Design State : Fully Placed
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Slice Logic Distribution
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3. Memory
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4. DSP
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5. IO and GT Specific
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6. Clocking
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7. Specific Feature
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8. Primitives
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9. Black Boxes
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10. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+-------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------------------+-------+-------+------------+-----------+-------+
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| Slice LUTs | 23324 | 0 | 0 | 53200 | 43.84 |
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| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
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| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
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| LUT as Distributed RAM | 558 | 0 | | | |
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| LUT as Shift Register | 1005 | 0 | | | |
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| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
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| Register as Flip Flop | 33794 | 0 | 0 | 106400 | 31.76 |
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| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
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| F7 Muxes | 1872 | 0 | 0 | 26600 | 7.04 |
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| F8 Muxes | 792 | 0 | 0 | 13300 | 5.95 |
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+----------------------------+-------+-------+------------+-----------+-------+
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* Warning! LUT value is adjusted to account for LUT combining.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 90 | Yes | - | Set |
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| 12487 | Yes | - | Reset |
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| 859 | Yes | Set | - |
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| 20367 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Slice Logic Distribution
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---------------------------
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+--------------------------------------------+-------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+--------------------------------------------+-------+-------+------------+-----------+-------+
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| Slice | 11328 | 0 | 0 | 13300 | 85.17 |
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| SLICEL | 7545 | 0 | | | |
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| SLICEM | 3783 | 0 | | | |
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| LUT as Logic | 21761 | 0 | 0 | 53200 | 40.90 |
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| using O5 output only | 0 | | | | |
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| using O6 output only | 17358 | | | | |
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| using O5 and O6 | 4403 | | | | |
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| LUT as Memory | 1563 | 0 | 0 | 17400 | 8.98 |
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| LUT as Distributed RAM | 558 | 0 | | | |
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| using O5 output only | 0 | | | | |
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| using O6 output only | 6 | | | | |
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| using O5 and O6 | 552 | | | | |
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| LUT as Shift Register | 1005 | 0 | | | |
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| using O5 output only | 7 | | | | |
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| using O6 output only | 185 | | | | |
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| using O5 and O6 | 813 | | | | |
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| Slice Registers | 33794 | 0 | 0 | 106400 | 31.76 |
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| Register driven from within the Slice | 15274 | | | | |
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| Register driven from outside the Slice | 18520 | | | | |
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| LUT in front of the register is unused | 14377 | | | | |
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| LUT in front of the register is used | 4143 | | | | |
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| Unique Control Sets | 1907 | | 0 | 13300 | 14.34 |
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+--------------------------------------------+-------+-------+------------+-----------+-------+
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* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
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3. Memory
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---------
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+-------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 105 | 0 | 0 | 140 | 75.00 |
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| RAMB36/FIFO* | 102 | 0 | 0 | 140 | 72.86 |
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| RAMB36E1 only | 102 | | | | |
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| RAMB18 | 6 | 0 | 0 | 280 | 2.14 |
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| RAMB18E1 only | 6 | | | | |
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+-------------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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4. DSP
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------
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+-----------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------+------+-------+------------+-----------+-------+
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| DSPs | 0 | 0 | 0 | 220 | 0.00 |
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+-----------+------+-------+------------+-----------+-------+
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5. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+--------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+--------+
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| Bonded IOB | 58 | 58 | 0 | 125 | 46.40 |
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| IOB Master Pads | 22 | | | | |
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| IOB Slave Pads | 34 | | | | |
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| IOB Flip Flops | 9 | 9 | | | |
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| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
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| Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
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| ILOGIC | 6 | 6 | 0 | 125 | 4.80 |
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| IFF_Register | 6 | 6 | | | |
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| OLOGIC | 3 | 3 | 0 | 125 | 2.40 |
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| OUTFF_Register | 3 | 3 | | | |
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+-----------------------------+------+-------+------------+-----------+--------+
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6. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
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| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
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| BUFR | 0 | 0 | 0 | 16 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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7. Specific Feature
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-------------------
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+-------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+-------+
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| BSCANE2 | 1 | 0 | 0 | 4 | 25.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+-------+
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8. Primitives
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-------------
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+----------+-------+----------------------+
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| Ref Name | Used | Functional Category |
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+----------+-------+----------------------+
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| FDRE | 20367 | Flop & Latch |
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| FDCE | 12487 | Flop & Latch |
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| LUT6 | 9778 | LUT |
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| LUT3 | 4324 | LUT |
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| LUT2 | 3478 | LUT |
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| LUT4 | 3448 | LUT |
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| LUT5 | 3330 | LUT |
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| MUXF7 | 1872 | MuxFx |
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| LUT1 | 1806 | LUT |
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| SRL16E | 1288 | Distributed Memory |
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| CARRY4 | 988 | CarryLogic |
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| FDSE | 859 | Flop & Latch |
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| RAMD32 | 840 | Distributed Memory |
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| MUXF8 | 792 | MuxFx |
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| SRLC32E | 528 | Distributed Memory |
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| RAMS32 | 270 | Distributed Memory |
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| BIBUF | 130 | IO |
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| RAMB36E1 | 102 | Block Memory |
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| FDPE | 90 | Flop & Latch |
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| IBUF | 32 | IO |
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| OBUFT | 27 | IO |
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| OBUF | 26 | IO |
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| RAMB18E1 | 6 | Block Memory |
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| SRLC16E | 2 | Distributed Memory |
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| BUFG | 2 | Clock |
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| PS7 | 1 | Specialized Resource |
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| BSCANE2 | 1 | Others |
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+----------+-------+----------------------+
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9. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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10. Instantiated Netlists
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-------------------------
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+------------------------------------+------+
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| Ref Name | Used |
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+------------------------------------+------+
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| c_add_s16_s32 | 3 |
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| axis_data_fifo_w8_d128 | 2 |
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| vio_cur_flt_state | 1 |
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| u_ila_0 | 1 |
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| fifo_generator_1 | 1 |
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| fifo_generator_0 | 1 |
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| design_a9_1_smartconnect_0_0 | 1 |
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| design_a9_1_rst_ps7_0_50M_0 | 1 |
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| design_a9_1_processing_system7_0_0 | 1 |
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| design_a9_1_axis_data_fifo_2_0 | 1 |
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| design_a9_1_axis_data_fifo_1_1 | 1 |
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| design_a9_1_axis_data_fifo_1_0 | 1 |
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| design_a9_1_axis_data_fifo_0_0 | 1 |
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| design_a9_1_axi_smc_0 | 1 |
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| design_a9_1_axi_quad_spi_0_0 | 1 |
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| design_a9_1_axi_gpio_1_0 | 1 |
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| design_a9_1_axi_gpio_0_0 | 1 |
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| design_a9_1_axi_dma_2_0 | 1 |
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| design_a9_1_axi_dma_1_1 | 1 |
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| design_a9_1_axi_dma_1_0 | 1 |
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| design_a9_1_axi_dma_0_0 | 1 |
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| design_a9_1_axi_bram_ctrl_6_0 | 1 |
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| design_a9_1_axi_bram_ctrl_5_0 | 1 |
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| design_a9_1_axi_bram_ctrl_4_0 | 1 |
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| design_a9_1_axi_bram_ctrl_3_1 | 1 |
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| design_a9_1_axi_bram_ctrl_3_0 | 1 |
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| design_a9_1_axi_bram_ctrl_2_0 | 1 |
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| design_a9_1_axi_bram_ctrl_1_0 | 1 |
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| design_a9_1_axi_bram_ctrl_0_0 | 1 |
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| design_a9_1_Z_IO_0 | 1 |
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| design_a9_1_ZCHECK_SPI_0 | 1 |
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| design_a9_1_STIM_SPI_0 | 1 |
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| design_a9_1_CHANN_SEL_0 | 1 |
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| design_a9_1_CHANN_EN_2 | 1 |
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| design_a9_1_CHANN_EN_1 | 1 |
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| design_a9_1_CHANN_EN_0 | 1 |
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| dbg_hub | 1 |
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+------------------------------------+------+
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