85 lines
2.1 KiB
Verilog
85 lines
2.1 KiB
Verilog
`timescale 1ns/1ps
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module channel_switch_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam T_CLK = 10 ; //ns
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localparam DATA_WIDTH = 64 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [64-1:0] data_0 ;
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reg [64-1:0] data_1 ;
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wire [64-1:0] state ;
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wire adg1414_spi_cs ;
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wire adg1414_spi_sclk ;
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wire adg1414_spi_mosi ;
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100;
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@ ( posedge clk );
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data_0 <= 64'h8000000000000002;
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while (1) begin
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@ ( posedge clk );
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// data_0 <= data_0 + 1'b1;
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#5_000;
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end
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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data_0 <= 64'h0000000000000000;
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data_1 <= 64'hFFFFFFFFFFFFFFFF;
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end
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endtask
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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channel_switch#
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(
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.CLK_PERIOD ( T_CLK )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( 1'b1 ),
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.data_sel ( 1'b0 ),
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.data_0 ( data_0 ),
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.data_1 ( data_1 ),
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.state ( state ),
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.sync ( adg1414_spi_cs ),
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.sclk ( adg1414_spi_sclk ),
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.sdin ( adg1414_spi_mosi ),
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.sdo ( 1'b0 )
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);
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endmodule |