70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
`timescale 1ns/1ps
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module led_ctrl_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam T_CLK = 10; //ns
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [3-1:0] cmd ;
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wire led ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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led_ctrl#
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(
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.CLK_PERIOD ( T_CLK )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.cmd ( cmd ),
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.led ( led )
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);
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100;
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cmd <= 3'b011;
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// #40_000
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// @ ( posedge clk );
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// $stop;
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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cmd <= 3'b000;
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end
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endtask
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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endmodule |