BSI-901-fpga-software/c64_pro.srcs/sources_1/rtl/.VSCodeCounter/2024-03-26_15-29-43/results.csv

1	filename	language	Verilog	VHDL	comment	blank	total
2	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\accel_top.v	Verilog	117	0	13	36	166
3	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\accel\lis2dw12.v	Verilog	197	0	10	31	238
4	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\c64pro_top.v	Verilog	364	0	44	78	486
5	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_arrange.v	Verilog	195	0	16	31	242
6	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_if.v	Verilog	149	0	18	27	194
7	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_mod.v	Verilog	113	0	13	29	155
8	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi - backup.v	Verilog	186	0	12	29	227
9	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi.v	Verilog	218	0	10	35	263
10	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\ads1299_spi_tb.v	Verilog	79	0	16	21	116
11	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_config.v	Verilog	118	0	16	32	166
12	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top.v	Verilog	204	0	21	52	277
13	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_top_tb.v	Verilog	158	0	88	40	286
14	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\eeg\eeg_upload.v	Verilog	147	0	13	29	189
15	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_config.v	Verilog	81	0	14	25	120
16	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\emg\emg_top.v	Verilog	44	0	17	17	78
17	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl.v	Verilog	58	0	10	12	80
18	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\led_ctrl_tb.v	Verilog	34	0	19	17	70
19	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top.v	Verilog	320	0	35	70	425
20	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\pl_top_tb.v	Verilog	505	0	77	116	698
21	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect.v	Verilog	180	0	14	30	224
22	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\cnv_res_collect_tb.v	Verilog	119	0	20	33	172
23	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.v	Verilog	74	0	16	21	111
24	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\dds_stim_16ch_tb.vhd	VHDL	0	307	135	49	491
25	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_mod.v	Verilog	84	0	7	19	110
26	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top.v	Verilog	337	0	27	86	450
27	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\rhs2116_top_tb.v	Verilog	367	0	26	83	476
28	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen.v	Verilog	154	0	22	31	207
29	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\sine_gen_tb.v	Verilog	129	0	18	42	189
30	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_event_collect.v	Verilog	74	0	10	14	98
31	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\stim_monitor.v	Verilog	105	0	13	14	132
32	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange.v	Verilog	174	0	18	31	223
33	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_arrange_tb.v	Verilog	268	0	19	62	349
34	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute.v	Verilog	120	0	13	26	159
35	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_distribute_tb.v	Verilog	114	0	16	24	154
36	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer.v	Verilog	60	0	10	15	85
37	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\trans_timer_tb.v	Verilog	55	0	15	19	89
38	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config.v	Verilog	351	0	82	74	507
39	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_config_tb.v	Verilog	321	0	36	101	458
40	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if.v	Verilog	268	0	25	46	339
41	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\rhs2116\transmit_if_tb.v	Verilog	172	0	39	58	269
42	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if.v	Verilog	136	0	13	25	174
43	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\adg1414_if_tb.v	Verilog	56	0	15	17	88
44	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch.v	Verilog	169	0	25	30	224
45	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\switch\channel_switch_tb.v	Verilog	52	0	16	17	85
46	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_detection.v	Verilog	21	0	1	7	29
47	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top.v	Verilog	137	0	15	32	184
48	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\trigger\trigger_top_tb.v	Verilog	45	0	15	16	76
49	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_config.v	Verilog	96	0	14	29	139
50	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_sort.v	Verilog	141	0	12	27	180
51	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\upload\upload_top.v	Verilog	254	0	15	45	314
52	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\breath_gen.v	Verilog	123	0	13	25	161
53	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\debouncing.v	Verilog	93	0	10	15	118
54	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\pwm_gen.v	Verilog	40	0	4	9	53
55	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master.v	Verilog	148	0	12	25	185
56	d:\projects\vivadoPrj\c64_pro\c64_pro.srcs\sources_1\rtl\utils\spi_full_duplex_master_tb.v	Verilog	79	0	16	21	116
57	Total	-	8403	307	1239	1945	11894