214 lines
7.0 KiB
Verilog
214 lines
7.0 KiB
Verilog
`timescale 1 ns / 1 ps
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module upload_config#
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(
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parameter CHANNLE_QTY = 64 ,
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parameter PRE_MSG_LEN = 24
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output reg [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output reg eeg_sel ,
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output reg protocol_sel ,
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output [ 8*PRE_MSG_LEN-1:0] pre_message_array ,
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output [ 8*CHANNLE_QTY-1:0] ch_mapping2pc_array ,
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output [ CHANNLE_QTY-1:0] upload_ch_array ,
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output reg [32-1:0] upload_round_qty_set,
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output reg [ 8-1:0] pre_message_length ,
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output reg reset_package_id ,
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output reg [32-1:0] package_overtime_ms
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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localparam BRAM_ADDR_SEL = 13'h0010;
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localparam BRAM_ADDR_ROUNDS_QTY = 13'h0014;
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localparam BRAM_ADDR_PRE_MSG_LTH = 13'h0018;
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localparam BRAM_ADDR_RESET_PACKAGE_ID = 13'h001C;
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localparam BRAM_ADDR_PACKAGE_OVERTIME = 13'h0020;
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localparam BRAM_ADDR_MESSAGE_END = 13'h0024;
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localparam BRAM_ADDR_PRE_MSG_START = 13'h0100;
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localparam BRAM_ADDR_PRE_MSG_MASK = 13'h1F00;
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localparam BRAM_ADDR_CH_MAP_START = 13'h0200;
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localparam BRAM_ADDR_CH_MAP_MASK = 13'h1F00;
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localparam BRAM_ADDR_UPLOAD_CH_START = 13'h0300;
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localparam BRAM_ADDR_UPLOAD_CH_MASK = 13'h1F00;
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localparam N = (CHANNLE_QTY+7)/8;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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wire bram_wr_valid ;
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wire bram_rd_valid ;
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reg [ 8-1:0] pre_message[0:PRE_MSG_LEN-1] ;
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reg [ 8-1:0] ch_mapping2pc[0:CHANNLE_QTY-1] ;
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reg [ 8-1:0] upload_ch[0:N-1] ;
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wire [8*N-1:0] upload_ch_array_w ;
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integer n;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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test_data <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
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test_data <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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eeg_sel <= 1'b0;
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protocol_sel <= 1'b0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_SEL ) ) begin
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eeg_sel <= bram_din[0];
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protocol_sel <= bram_din[1];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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upload_round_qty_set <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_ROUNDS_QTY ) )
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upload_round_qty_set <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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pre_message_length <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PRE_MSG_LTH ) )
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pre_message_length <= bram_din[7:0];
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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reset_package_id <= 1'b0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_RESET_PACKAGE_ID ) )
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reset_package_id <= 1'b1;
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else
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reset_package_id <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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package_overtime_ms <= 10;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PACKAGE_OVERTIME ) )
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package_overtime_ms <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<PRE_MSG_LEN; n=n+1) begin
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pre_message[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_PRE_MSG_MASK) == BRAM_ADDR_PRE_MSG_START ) ) begin
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pre_message[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:pre_message[{bram_addr[7:2],2'b00}];
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pre_message[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:pre_message[{bram_addr[7:2],2'b01}];
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pre_message[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:pre_message[{bram_addr[7:2],2'b10}];
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pre_message[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:pre_message[{bram_addr[7:2],2'b11}];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<CHANNLE_QTY; n=n+1) begin
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ch_mapping2pc[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_CH_MAP_MASK) == BRAM_ADDR_CH_MAP_START ) ) begin
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ch_mapping2pc[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:ch_mapping2pc[{bram_addr[7:2],2'b00}];
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ch_mapping2pc[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:ch_mapping2pc[{bram_addr[7:2],2'b01}];
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ch_mapping2pc[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:ch_mapping2pc[{bram_addr[7:2],2'b10}];
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ch_mapping2pc[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:ch_mapping2pc[{bram_addr[7:2],2'b11}];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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for(n=0; n<N; n=n+1) begin
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upload_ch[n] <= 0;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_UPLOAD_CH_MASK) == BRAM_ADDR_UPLOAD_CH_START ) ) begin
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upload_ch[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:upload_ch[{bram_addr[7:2],2'b00}];
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upload_ch[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:upload_ch[{bram_addr[7:2],2'b01}];
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upload_ch[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:upload_ch[{bram_addr[7:2],2'b10}];
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upload_ch[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:upload_ch[{bram_addr[7:2],2'b11}];
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end
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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bram_dout <= 0;
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end else if ( bram_rd_valid ) begin
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if ( bram_addr == BRAM_ADDR_TEST_RO )
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bram_dout <= 32'h12340004;
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if ( bram_addr == BRAM_ADDR_TEST_RW )
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bram_dout <= test_data;
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end
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign bram_wr_valid = bram_en && (bram_we != 4'h0);
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assign bram_rd_valid = bram_en && (bram_we == 4'h0);
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generate
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for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pack_pre_msg
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assign pre_message_array[8*i+7 : 8*i] = pre_message[i];
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end
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endgenerate
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generate
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for(i=0;i<CHANNLE_QTY;i=i+1) begin : pack_ch_mapping
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assign ch_mapping2pc_array[8*i+7 : 8*i] = ch_mapping2pc[i];
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end
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endgenerate
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generate
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for(i=0;i<N;i=i+1) begin : pack_upload_channel
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assign upload_ch_array_w[8*i+7 : 8*i] = upload_ch[i];
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end
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endgenerate
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generate
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for(i=0;i<CHANNLE_QTY;i=i+1) begin : link_upload_channel
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assign upload_ch_array[i] = upload_ch_array_w[i];
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end
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endgenerate
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endmodule
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