BSI-901-fpga-software/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if_tb.v

 `timescale 1ns/1ps
 
module transmit_ctrl_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter 		T_CLK 			= 20;		//ns
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk						;
	reg								rst_n					;
	
	reg								enable					;
	reg								enable_record			;
	reg								enable_stim				;
	
	reg		[32-1:0]				update_period			;
	wire							repeat_en				;
	wire							trans					;
		
	//------------------------------------------ ps command input
	reg								ps_cmd_valid			;
	reg		[32-1:0]				ps_cmd_data				;
	wire							ps_cmd_ready			;
	wire							ps_cmd_res_en			;
	wire	[32-1:0]				ps_cmd_res				;

	//------------------------------------------ conver input
	wire	[32*16-1:0]				cnv_cmd_array			;
	reg		[ 8-1:0]				cnv_cmd_lth				;

	//------------------------------------------ auxiliary command
	reg		[32-1:0]				auxiliary_cmd_1			;
	reg		[32-1:0]				auxiliary_cmd_2			;

	//------------------------------------------ stim input
	reg		[ 8-1:0]				current_trim			;
	reg		[ 9*32-1:0]				sine_wave_data			;

	reg								stim_fifo_empty			;
	reg		[32-1:0]				stim_fifo_dout			;
	wire							stim_fifo_rd_en			;

	//------------------------------------------ polarity command align
	wire							stim_appear_flag		;
	wire							stim_polarity_ready		;
	reg								stim_polarity_trans		;

	//------------------------------------------ record output
	wire	[32-1:0]				cnv_res_tdata			;
	wire							cnv_res_tlast			;
	reg								cnv_res_tready			;
	wire							cnv_res_tvalid			;

	//------------------------------------------ Trigger
	wire							trigger_in				;
	wire							trigger_out				;

	//------------------------------------------ device spi
	wire							cs						;
	wire							sclk					;
	wire							mosi					;
	wire							miso					;
	
	
	reg		[32-1:0]				cnv_cmd[0:15]			;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	trans_timer u_trans_timer
		(
			.clk				( clk 				),
			.rst_n				( rst_n 			),
			
			.enable				( enable 			),
			.update_period		( update_period		),
			
			.update				( repeat_en   		),
			.trans				( trans   			)
		);
	
	transmit_if# 
		(
			.CLK_PERIOD			( 20				),
			.CHIPSET			( 0					),
			.STIM_POL_REG_ADDR	( 8'd44				),
			.POS_CUR_REG_ADDR	( 8'd64				),
			.NEG_CUR_REG_ADDR	( 8'd96				)
		)
	DUT
		(
			.clk				( clk				),
			.rst_n				( rst_n				),
			
			.enable				( enable			),
			.enable_record		( enable_record		),	//record_div_en
			.enable_stim		( enable_stim		),
			
			.repeat_en			( repeat_en			),
			.transmit_en		( trans				),
			
			//------------------------------------------ ps command input
			.ps_cmd_valid		( ps_cmd_valid		),
			.ps_cmd_data		( ps_cmd_data		),
			.ps_cmd_ready		( ps_cmd_ready		),
			.ps_cmd_res_en		( ps_cmd_res_en		),
			.ps_cmd_res			( ps_cmd_res		),
			
			//------------------------------------------ conver input
			.cnv_cmd_array		( cnv_cmd_array		),
			.cnv_cmd_lth		( cnv_cmd_lth		),
			
			//------------------------------------------ auxiliary command
			.auxiliary_cmd_1	( auxiliary_cmd_1	),
			.auxiliary_cmd_2	( auxiliary_cmd_2	),
			
			//------------------------------------------ stim input
			.current_trim		( current_trim		),
			.wave_data_array	( sine_wave_data	),
			
			.stim_fifo_empty	( stim_fifo_empty	),
			.stim_fifo_dout		( stim_fifo_dout	),
			.stim_fifo_rd_en	( stim_fifo_rd_en	),
			
			//------------------------------------------ polarity command align
			.stim_data_appear	( stim_appear_flag		),
			.stim_polarity_appear( stim_polarity_ready	),
			.stim_polarity_trans( stim_polarity_trans	),
			
			//------------------------------------------ record output
			.cnv_res_tdata		( cnv_res_tdata		),
			.cnv_res_tlast		( cnv_res_tlast		),
			.cnv_res_tready		( cnv_res_tready	),
			.cnv_res_tvalid		( cnv_res_tvalid	),
			
			//------------------------------------------ Trigger
			.trigger_in			( trigger_in		),
			.trigger_out		( trigger_out		),
			
			//------------------------------------------ device spi
			.cs					( cs				),
			.sclk				( sclk				),
			.mosi				( mosi				),
			.miso				( miso				)
		);
		
	rhs2116_mod u_rhs2116_mod
		(
			.cs					( cs 				),
			.sclk				( sclk 				),
			.mosi				( mosi 				),
			.miso				( miso				)
		);
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
		#100
		@ ( posedge clk );
		enable_record	<= 1'b1			;
	//	enable_stim		<= 1'b0			;
		#100
		@ ( posedge clk ) enable <= 1'b1;
		
		
		#1_000_000
		@ ( posedge clk ) enable <= 1'b0;
		
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0			;
			rst_n			<= 1'b0			;
			
			enable			<= 1'b0			;
			update_period	<= 30_000/20	;	//30_000 ns
			
			
			
			
			enable_record	<= 1'b0			;
			enable_stim		<= 1'b0			;
					
			//------------------------------------------ ps command input
			ps_cmd_valid	<= 1'b0			;
			ps_cmd_data		<= 0			;

			//------------------------------------------ conver input
			cnv_cmd_lth		<= 8'd16		;
			cnv_cmd[ 0]		<= 32'h00000000	;
			cnv_cmd[ 1]		<= 32'h00010000	;
			cnv_cmd[ 2]		<= 32'h00020000	;
			cnv_cmd[ 3]		<= 32'h00030000	;
			cnv_cmd[ 4]		<= 32'h00040000	;
			cnv_cmd[ 5]		<= 32'h00050000	;
			cnv_cmd[ 6]		<= 32'h00090000	;
			cnv_cmd[ 7]		<= 32'h00080000	;
			cnv_cmd[ 8]		<= 32'h00070000	;
			cnv_cmd[ 9]		<= 32'h00060000	;
			cnv_cmd[10]		<= 32'h000A0000	;
			cnv_cmd[11]		<= 32'h000B0000	;
			cnv_cmd[12]		<= 32'h000C0000	;
			cnv_cmd[13]		<= 32'h000D0000	;
			cnv_cmd[14]		<= 32'h000E0000	;
			cnv_cmd[15]		<= 32'h000F0000	;

			//------------------------------------------ auxiliary command
			auxiliary_cmd_1	<= 32'hC0280000	;
			auxiliary_cmd_2	<= 32'hC0320000	;

			//------------------------------------------ stim input
			current_trim	<= 0			;
			sine_wave_data	<= 0			;

			stim_fifo_empty	<= 1'b1			;
			stim_fifo_dout	<= 0			;

			//------------------------------------------ polarity command align
			stim_polarity_trans	<= 1'b0		;

			//------------------------------------------ record output
			cnv_res_tready <= 1'b1			;
			
		end
	endtask
	
	task write_fifo;
		input [32-1:0]	tdata;
		input			tlast;
		begin
			s_axis_tdata	<= tdata;
			s_axis_tvalid	<= 1'b1;
			s_axis_tlast	<= tlast;
			@ ( posedge clk );
			while(~s_axis_tready) @ ( posedge clk );
			if(tlast) begin
				s_axis_tvalid	<= 1'b0;
				s_axis_tlast	<= 1'b0;
			end
		end
	endtask
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	genvar i;
	
	generate
		for(i=0;i<16;i=i+1) begin : pack
			assign cnv_cmd_array[32*i+31 : 32*i] = cnv_cmd[i];
		end
	endgenerate
	
	
endmodule