313 lines
21 KiB
Plaintext
313 lines
21 KiB
Plaintext
# do {pl_top_tb_compile.do}
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/work".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xilinx_vip".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xpm".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axis_infrastructure_v1_1_0".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axis_data_fifo_v2_0_10".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xil_defaultlib".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_utils_v3_0_10".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_pipe_v3_0_6".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_bram18k_v3_0_6".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/mult_gen_v12_0_18".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axi_utils_v2_0_6".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6".
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# ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/dds_compiler_v6_0_22".
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xilinx_vip modelsim_lib/msim/xilinx_vip
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xpm modelsim_lib/msim/xpm
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap axis_infrastructure_v1_1_0 modelsim_lib/msim/axis_infrastructure_v1_1_0
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap axis_data_fifo_v2_0_10 modelsim_lib/msim/axis_data_fifo_v2_0_10
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap mult_gen_v12_0_18 modelsim_lib/msim/mult_gen_v12_0_18
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_dsp48_wrapper_v3_0_4 modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_dsp48_addsub_v3_0_6 modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap xbip_dsp48_multadd_v3_0_6 modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap dds_compiler_v6_0_22 modelsim_lib/msim/dds_compiler_v6_0_22
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# Modifying modelsim.ini
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:52 on Jul 29,2024
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# vlog -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -work xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv
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# -- Skipping interface axi4stream_vip_axi4streampc
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# -- Skipping interface axi_vip_axi4pc
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# -- Skipping package xil_common_vip_pkg
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# -- Skipping package axi4stream_vip_pkg
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# -- Skipping package axi_vip_pkg
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# -- Skipping interface axi4stream_vip_if
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# -- Skipping interface axi_vip_if
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# -- Skipping interface clk_vip_if
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# -- Skipping interface rst_vip_if
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# -- Skipping package axi4stream_vip_axi4streampc_sv_unit
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#
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# Top level modules:
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# --none--
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# End time: 14:48:52 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:52 on Jul 29,2024
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# vlog -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -work xpm "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
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# -- Skipping module xpm_cdc_single
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# -- Skipping module xpm_cdc_gray
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# -- Skipping module xpm_cdc_handshake
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# -- Skipping module xpm_cdc_pulse
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# -- Skipping module xpm_cdc_array_single
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# -- Skipping module xpm_cdc_sync_rst
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# -- Skipping module xpm_cdc_async_rst
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# -- Skipping module xpm_cdc_low_latency_handshake
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# -- Skipping module xpm_fifo_base
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# -- Skipping module xpm_fifo_rst
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# -- Skipping module xpm_counter_updn
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# -- Skipping module xpm_fifo_reg_vec
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# -- Skipping module xpm_fifo_reg_bit
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# -- Skipping module xpm_reg_pipe_bit
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# -- Skipping module xpm_fifo_sync
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# -- Skipping module xpm_fifo_async
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# -- Skipping module xpm_fifo_axis
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# -- Skipping module xpm_fifo_axif
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# -- Skipping module xpm_fifo_axil
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# -- Skipping module xpm_fifo_axi_reg_slice
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# -- Skipping module xpm_memory_base
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# -- Skipping module asym_bwe_bb
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# -- Skipping module xpm_memory_dpdistram
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# -- Skipping module xpm_memory_dprom
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# -- Skipping module xpm_memory_sdpram
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# -- Skipping module xpm_memory_spram
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# -- Skipping module xpm_memory_sprom
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# -- Skipping module xpm_memory_tdpram
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#
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# Top level modules:
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# xpm_cdc_handshake
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# xpm_cdc_pulse
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# xpm_cdc_array_single
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# xpm_cdc_async_rst
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# xpm_cdc_low_latency_handshake
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# xpm_fifo_sync
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# xpm_fifo_async
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# xpm_fifo_axis
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# xpm_fifo_axif
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# xpm_fifo_axil
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# xpm_memory_dpdistram
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# xpm_memory_dprom
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# xpm_memory_sdpram
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# xpm_memory_spram
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# xpm_memory_sprom
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# xpm_memory_tdpram
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# End time: 14:48:53 on Jul 29,2024, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:54 on Jul 29,2024
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# vcom -93 -work xpm C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling package VCOMPONENTS
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# End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:54 on Jul 29,2024
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# vlog -incr -mfcu -work axis_infrastructure_v1_1_0 "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v
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# -- Skipping module axis_infrastructure_v1_1_0_mux_enc
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# -- Skipping module axis_infrastructure_v1_1_0_util_aclken_converter
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# -- Skipping module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
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# -- Skipping module axis_infrastructure_v1_1_0_util_axis2vector
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# -- Skipping module axis_infrastructure_v1_1_0_util_vector2axis
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# -- Skipping module axis_infrastructure_v1_1_0_clock_synchronizer
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# -- Skipping module axis_infrastructure_v1_1_0_cdc_handshake
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#
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# Top level modules:
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# axis_infrastructure_v1_1_0_mux_enc
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# axis_infrastructure_v1_1_0_util_aclken_converter_wrapper
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# axis_infrastructure_v1_1_0_clock_synchronizer
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# axis_infrastructure_v1_1_0_cdc_handshake
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# End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:54 on Jul 29,2024
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# vlog -incr -mfcu -work axis_data_fifo_v2_0_10 "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.ip_user_files/ipstatic/hdl/axis_data_fifo_v2_0_vl_rfs.v
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# -- Skipping module axis_data_fifo_v2_0_10_top
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#
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# Top level modules:
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# axis_data_fifo_v2_0_10_top
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# End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:54 on Jul 29,2024
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# vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/sim/axis_data_fifo_w8_d128.v
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# -- Skipping module axis_data_fifo_w8_d128
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#
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# Top level modules:
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# axis_data_fifo_w8_d128
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# End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:54 on Jul 29,2024
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# vcom -93 -work xbip_utils_v3_0_10 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:48:55 on Jul 29,2024, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:56 on Jul 29,2024
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# vcom -93 -work xbip_pipe_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:48:56 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:56 on Jul 29,2024
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# vcom -93 -work xbip_bram18k_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:48:58 on Jul 29,2024, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:48:58 on Jul 29,2024
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# vcom -93 -work mult_gen_v12_0_18 ../../../../c64_pro.ip_user_files/ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:00 on Jul 29,2024, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:00 on Jul 29,2024
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# vcom -93 -work xil_defaultlib ../../../../c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/sim/mult_gen_au8_bu9_p8.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package NUMERIC_STD
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# -- Compiling entity mult_gen_au8_bu9_p8
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# -- Compiling architecture mult_gen_au8_bu9_p8_arch of mult_gen_au8_bu9_p8
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# End time: 14:49:00 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:01 on Jul 29,2024
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# vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v
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# -- Skipping module axis_data_fifo_w32_d32
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#
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# Top level modules:
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# axis_data_fifo_w32_d32
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# End time: 14:49:01 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:01 on Jul 29,2024
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# vcom -93 -work axi_utils_v2_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:01 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:01 on Jul 29,2024
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# vcom -93 -work xbip_dsp48_wrapper_v3_0_4 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:03 on Jul 29,2024, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:03 on Jul 29,2024
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# vcom -93 -work xbip_dsp48_addsub_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:04 on Jul 29,2024, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:04 on Jul 29,2024
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# vcom -93 -work xbip_dsp48_multadd_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:06 on Jul 29,2024, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:06 on Jul 29,2024
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# vcom -93 -work dds_compiler_v6_0_22 ../../../../c64_pro.ip_user_files/ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd
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# -- Loading package STANDARD
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# End time: 14:49:08 on Jul 29,2024, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:09 on Jul 29,2024
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# vcom -93 -work xil_defaultlib ../../../../c64_pro.gen/sources_1/ip/dds_stim_16ch/sim/dds_stim_16ch.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package NUMERIC_STD
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# -- Compiling entity dds_stim_16ch
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# -- Compiling architecture dds_stim_16ch_arch of dds_stim_16ch
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# End time: 14:49:09 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:09 on Jul 29,2024
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# vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/sim/axis_data_fifo_w32_d16.v ../../../../c64_pro.srcs/sources_1/rtl/accel/accel_top.v ../../../../c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v ../../../../c64_pro.srcs/sources_1/rtl/utils/debouncing.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v ../../../../c64_pro.srcs/sources_1/rtl/emg/emg_top.v ../../../../c64_pro.srcs/sources_1/rtl/pl_top.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v ../../../../c64_pro.srcs/sources_1/rtl/utils/run_time.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v ../../../../c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v ../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v ../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_config.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_sort.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_top.v ../../../../c64_pro.srcs/sources_1/rtl/pl_top_tb.v
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# -- Skipping module axis_data_fifo_w32_d16
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# -- Skipping module accel_top
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# -- Skipping module adg1414_if
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# -- Skipping module ads1299_arrange
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# -- Skipping module ads1299_if
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# -- Skipping module ads1299_mod
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# -- Skipping module ads1299_spi
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# ** Warning: ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v(27): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
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# ** Warning: ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v(28): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
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# -- Skipping module channel_switch
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# -- Skipping module cnv_res_collect
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# -- Skipping module debouncing
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# -- Skipping module eeg_config
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# -- Skipping module eeg_top
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# -- Skipping module eeg_upload
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# -- Skipping module emg_top
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|
# -- Skipping module pl_top
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# -- Skipping module rhs2116_mod
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# -- Skipping module rhs2116_top
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# -- Skipping module run_time
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# -- Skipping module sine_gen
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# -- Skipping module spi_full_duplex_master
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# -- Skipping module stim_event_collect
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# -- Skipping module stim_monitor
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# -- Skipping module trans_arrange
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# -- Skipping module trans_distribute
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# -- Skipping module trans_timer
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# -- Skipping module transmit_config
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# -- Skipping module transmit_if
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# -- Skipping module trigger_detection
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# -- Skipping module trigger_top
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# -- Compiling module upload_config
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# -- Compiling module upload_protocol_intan
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# -- Skipping module upload_protocol_ql
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# -- Compiling module upload_sort
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# -- Skipping module upload_top
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# -- Compiling module pl_top_tb
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#
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# Top level modules:
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# pl_top_tb
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# End time: 14:49:09 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 2
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# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
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# Start time: 14:49:10 on Jul 29,2024
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# vlog -work xil_defaultlib glbl.v
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# -- Compiling module glbl
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#
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# Top level modules:
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# glbl
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# End time: 14:49:10 on Jul 29,2024, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
|