184 lines
4.8 KiB
Verilog
184 lines
4.8 KiB
Verilog
`timescale 1 ns / 1 ps
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module trigger_top#
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(
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parameter CLK_PERIOD = 10
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)
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(
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input clk ,
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input rst_n ,
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input trigger_reset ,
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input [32-1:0] trigger_in_int ,
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input [32-1:0] trigger_in_ext ,
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output [32-1:0] m_trigger_tdata ,
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output m_trigger_tvalid ,
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input m_trigger_tready ,
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output reg error_overflow
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam CLKS = 10 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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wire [32-1:0] trigger_in_ext_t ;
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wire trigger_1_tvalid ;
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wire [32-1:0] trigger_1_tdata ;
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wire trigger_2_tvalid ;
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wire [32-1:0] trigger_2_tdata ;
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reg trigger_1_tvalid_r ;
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reg [32-1:0] trigger_1_tdata_r ;
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reg trigger_2_tvalid_r ;
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reg [32-1:0] trigger_2_tdata_r ;
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reg trigger_2_tvalid_rr ;
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reg [32-1:0] trigger_2_tdata_rr ;
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reg [32-1:0] trigger_collect_tdata ;
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reg trigger_collect_tvalid ;
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wire trigger_collect_tready ;
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reg [ 8-1:0] clk_cnt ;
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reg s_axis_aresetn ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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debouncing#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.DATA_WIDTH ( 32 ),
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.DELAY1_US ( 30 ),
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.DELAY2_US ( 50 )
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)
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u_debouncing_ext
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.data_in ( trigger_in_ext ),
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.data_out ( trigger_in_ext_t )
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);
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trigger_detection u_trigger_detection_int
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trigger_in ( trigger_in_int ),
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.trigger_tdata ( trigger_1_tdata ),
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.trigger_tvalid ( trigger_1_tvalid )
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);
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trigger_detection u_trigger_detection_ext
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trigger_in ( trigger_in_ext_t ),
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.trigger_tdata ( trigger_2_tdata ),
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.trigger_tvalid ( trigger_2_tvalid )
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);
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axis_data_fifo_w32_d16 u_trigger_fifo
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(
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.s_axis_aresetn ( s_axis_aresetn ),
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.s_axis_aclk ( clk ),
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.s_axis_tvalid ( trigger_collect_tvalid),
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.s_axis_tready ( trigger_collect_tready),
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.s_axis_tdata ( trigger_collect_tdata ),
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.m_axis_tvalid ( m_trigger_tvalid ),
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.m_axis_tready ( m_trigger_tready ),
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.m_axis_tdata ( m_trigger_tdata )
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);
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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trigger_1_tvalid_r <= 1'b0;
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trigger_1_tdata_r <= 0;
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trigger_2_tvalid_r <= 1'b0;
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trigger_2_tdata_r <= 0;
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end else begin
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trigger_1_tvalid_r <= trigger_1_tvalid;
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trigger_1_tdata_r <= trigger_1_tdata;
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trigger_2_tvalid_r <= trigger_2_tvalid;
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trigger_2_tdata_r <= trigger_2_tdata;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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trigger_2_tvalid_rr <= 1'b0;
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trigger_2_tdata_rr <= 0;
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end else if (trigger_1_tvalid_r && trigger_2_tvalid_r) begin
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trigger_2_tvalid_rr <= trigger_2_tvalid_r;
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trigger_2_tdata_rr <= trigger_2_tdata_r;
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end else begin
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trigger_2_tvalid_rr <= 1'b0;
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trigger_2_tdata_rr <= 0;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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trigger_collect_tvalid <= 1'b0;
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trigger_collect_tdata <= 0;
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end else if (trigger_1_tvalid_r || trigger_2_tvalid_r || trigger_2_tvalid_rr) begin
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trigger_collect_tvalid <= 1'b1;
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trigger_collect_tdata <= trigger_1_tvalid_r? trigger_1_tdata_r:
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(trigger_2_tvalid_r? trigger_2_tdata_r:
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(trigger_2_tvalid_rr? trigger_2_tdata_rr:
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trigger_collect_tdata));
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end else
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trigger_collect_tvalid <= 1'b0;
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end
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//trigger clear
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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clk_cnt <= 0;
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else if (clk_cnt != CLKS)
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clk_cnt = clk_cnt + 1'b1;
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else if (trigger_reset)
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clk_cnt <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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s_axis_aresetn <= 1'b1;
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else if (clk_cnt != CLKS)
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s_axis_aresetn <= 1'b0;
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else
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s_axis_aresetn <= 1'b1;
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end
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//error: trigger overflow
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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error_overflow <= 1'b0;
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else if (trigger_collect_tvalid && ~trigger_collect_tready)
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error_overflow <= 1'b1;
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else
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error_overflow <= 1'b0;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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endmodule
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