1272 lines
181 KiB
Plaintext
1272 lines
181 KiB
Plaintext
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*** Running vivado
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with args -log c64pro_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
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****** Vivado v2023.1 (64-bit)
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**** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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source c64pro_top.tcl -notrace
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create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1391.258 ; gain = 159.383
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add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1469.812 ; gain = 39.594
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Command: synth_design -top c64pro_top -part xc7z010clg400-2
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: [Device 21-403] Loading part xc7z010clg400-2
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INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
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INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
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INFO: [Synth 8-7075] Helper process launched with PID 8108
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2290.688 ; gain = 409.566
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'c64pro_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/c64pro_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_wrapper' [D:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v:13]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:13]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_1_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_1_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_2_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_2_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_2_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_2_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_3_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_3_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_3_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_3_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_4_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_4_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_4_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_bram_ctrl_4_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_dma_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_dma_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'mm2s_prmry_reset_out_n' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:779]
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WARNING: [Synth 8-7071] port 'm_axis_mm2s_tkeep' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:779]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:779]
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WARNING: [Synth 8-7023] instance 'axi_dma_0' of module 'design_a9_1_axi_dma_0_0' has 40 connections declared, but only 37 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:779]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_1_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_dma_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_1_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_dma_1_0_stub.v:6]
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WARNING: [Synth 8-7071] port 's2mm_prmry_reset_out_n' of module 'design_a9_1_axi_dma_1_0' is unconnected for instance 'axi_dma_1' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:817]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_1_0' is unconnected for instance 'axi_dma_1' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:817]
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WARNING: [Synth 8-7023] instance 'axi_dma_1' of module 'design_a9_1_axi_dma_1_0' has 43 connections declared, but only 41 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:817]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_gpio_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_gpio_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_gpio_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_gpio_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_iic_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_iic_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_iic_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_iic_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'gpo' of module 'design_a9_1_axi_iic_0_0' is unconnected for instance 'axi_iic_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:882]
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WARNING: [Synth 8-7023] instance 'axi_iic_0' of module 'design_a9_1_axi_iic_0_0' has 27 connections declared, but only 26 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:882]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_iic_1_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_iic_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_iic_1_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_iic_1_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'gpo' of module 'design_a9_1_axi_iic_1_0' is unconnected for instance 'axi_iic_1' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:909]
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WARNING: [Synth 8-7023] instance 'axi_iic_1' of module 'design_a9_1_axi_iic_1_0' has 27 connections declared, but only 26 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:909]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_smc_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_smc_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_smc_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axi_smc_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'M01_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M01_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M04_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M04_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M06_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M06_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M06_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M07_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M07_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M07_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M08_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7071] port 'M08_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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WARNING: [Synth 8-7023] instance 'axi_smc' of module 'design_a9_1_axi_smc_0' has 230 connections declared, but only 218 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:936]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axis_data_fifo_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axis_data_fifo_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_1_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axis_data_fifo_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_1_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_axis_data_fifo_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_processing_system7_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_processing_system7_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_processing_system7_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_processing_system7_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'USB0_PORT_INDCTL' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'USB0_VBUS_PWRSELECT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_BID' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RID' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RCOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_WCOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RACOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_WACOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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WARNING: [Synth 8-7023] instance 'processing_system7_0' of module 'design_a9_1_processing_system7_0_0' has 111 connections declared, but only 103 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1180]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_rst_ps7_0_50M_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_rst_ps7_0_50M_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_rst_ps7_0_50M_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_rst_ps7_0_50M_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'mb_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1284]
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WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1284]
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WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1284]
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WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1284]
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WARNING: [Synth 8-7023] instance 'rst_ps7_0_50M' of module 'design_a9_1_rst_ps7_0_50M_0' has 10 connections declared, but only 6 given [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1284]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_smartconnect_0_0' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_smartconnect_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_smartconnect_0_0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/design_a9_1_smartconnect_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_xlconcat_0_0' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/synth/design_a9_1_xlconcat_0_0.v:53]
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INFO: [Synth 8-6157] synthesizing module 'xlconcat_v2_1_4_xlconcat' [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v:14]
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INFO: [Synth 8-6155] done synthesizing module 'xlconcat_v2_1_4_xlconcat' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v:14]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_xlconcat_0_0' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/synth/design_a9_1_xlconcat_0_0.v:53]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1' (0#1) [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:13]
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INFO: [Synth 8-6157] synthesizing module 'IOBUF' [C:/Xilinx/Vivado/2023.1/scripts/rt/data/unisim_comp.v:76334]
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INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [C:/Xilinx/Vivado/2023.1/scripts/rt/data/unisim_comp.v:76334]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_wrapper' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v:13]
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INFO: [Synth 8-6157] synthesizing module 'pl_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v:3]
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Parameter VERSION bound to: 536870917 - type: integer
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Parameter CLK_FREQ bound to: 100 - type: integer
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter RSH2116_QTY bound to: 4 - type: integer
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Parameter ADS1299_QTY bound to: 8 - type: integer
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Parameter ADS1299_SPI_QTY bound to: 4 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'trigger_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'debouncing' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/debouncing.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter DATA_WIDTH bound to: 32 - type: integer
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Parameter DELAY1_US bound to: 30 - type: integer
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Parameter DELAY2_US bound to: 50 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'debouncing' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/debouncing.v:3]
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INFO: [Synth 8-6157] synthesizing module 'trigger_detection' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'trigger_detection' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v:3]
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INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w32_d16' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w32_d16_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w32_d16' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w32_d16_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'trigger_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'rhs2116_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v:3]
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Parameter VERSION bound to: 536870917 - type: integer
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter SPI_CLK_DIV bound to: 4 - type: integer
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Parameter SPI_TRANS_PERIOD bound to: 1500 - type: integer
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Parameter CHIPSET_QTY bound to: 4 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'trans_arrange' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v:3]
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Parameter REG_ADDR_STIM_POL bound to: 8'b00101100
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Parameter REG_ADDR_POS_CUR bound to: 8'b01000000
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Parameter REG_ADDR_NEG_CUR bound to: 8'b01100000
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INFO: [Synth 8-6157] synthesizing module 'mult_gen_au8_bu9_p8' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/mult_gen_au8_bu9_p8_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'mult_gen_au8_bu9_p8' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/mult_gen_au8_bu9_p8_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'trans_arrange' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v:3]
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INFO: [Synth 8-6157] synthesizing module 'transmit_if' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v:3]
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Parameter SPI_CLK_DIV bound to: 4 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 32 - type: integer
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Parameter CH_OF_CHIPSET bound to: 16 - type: integer
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Parameter CMD_CONVERT bound to: 2'b00
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Parameter CMD_EXTEND bound to: 2'b01
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Parameter CMD_WRITE bound to: 2'b10
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Parameter CMD_READ bound to: 2'b11
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Parameter REG_ADDR_MONITOR bound to: 8'b00101000
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INFO: [Synth 8-6157] synthesizing module 'spi_full_duplex_master' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v:3]
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Parameter CLK_DIV bound to: 4 - type: integer
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Parameter DATA_WIDTH bound to: 32 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'spi_full_duplex_master' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'transmit_if' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v:3]
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INFO: [Synth 8-6157] synthesizing module 'transmit_config' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:3]
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Parameter CHIPSET_QTY bound to: 4 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'transmit_config' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'trans_timer' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter SPI_TRANS_PERIOD bound to: 1500 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'trans_timer' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sine_gen' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v:3]
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INFO: [Synth 8-6157] synthesizing module 'dds_stim_16ch' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/dds_stim_16ch_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'dds_stim_16ch' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/dds_stim_16ch_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'sine_gen' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v:3]
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INFO: [Synth 8-6157] synthesizing module 'trans_distribute' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v:3]
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INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w32_d32' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w32_d32_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w32_d32' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w32_d32_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'trans_distribute' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v:3]
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INFO: [Synth 8-6157] synthesizing module 'cnv_res_collect' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:3]
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Parameter CHIPSET_QTY bound to: 4 - type: integer
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Parameter CH_OF_CHIPSET bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'cnv_res_collect' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:3]
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INFO: [Synth 8-6157] synthesizing module 'stim_event_collect' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v:3]
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Parameter CHIPSET_QTY bound to: 4 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'stim_event_collect' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v:3]
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INFO: [Synth 8-6157] synthesizing module 'stim_monitor' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'stim_monitor' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'rhs2116_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_arrange' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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Parameter SPI_TRANS_PERIOD bound to: 2000 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_arrange' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ads1299_if' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v:3]
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Parameter SPI_CLK_DIV bound to: 3 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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Parameter SPI_SLAVE_QTY bound to: 2 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_spi' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CLK_DIV bound to: 3 - type: integer
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Parameter DATA_WIDTH bound to: 8 - type: integer
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Parameter NO_OF_SLAVES bound to: 2 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_spi' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_if' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_config' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:3]
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Parameter SPIS_QTY bound to: 4 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'eeg_config' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_upload' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHIPSET_QTY bound to: 4 - type: integer
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Parameter CH_OF_CHIPSET bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'eeg_upload' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'eeg_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'emg_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/emg/emg_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'emg_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/emg/emg_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'accel_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/accel/accel_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'accel_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/accel/accel_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'channel_switch' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/channel_switch.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'adg1414_if' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CLK_DIV bound to: 20 - type: integer
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Parameter DATA_WIDTH bound to: 64 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'adg1414_if' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'channel_switch' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/switch/channel_switch.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'run_time' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/run_time.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'run_time' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/run_time.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_config' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_config.v:3]
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Parameter CHANNLE_QTY bound to: 64 - type: integer
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Parameter PRE_MSG_LEN bound to: 128 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_config' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_sort' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHANNLE_QTY bound to: 64 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w8_d128_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/.Xil/Vivado-52932-840-5CG14025H4/realtime/axis_data_fifo_w8_d128_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'upload_sort' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_protocol_ql' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter PRE_MSG_LEN bound to: 128 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_protocol_ql' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:3]
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WARNING: [Synth 8-7071] port 'interrupt' of module 'upload_protocol_ql' is unconnected for instance 'u_upload_protocol_ql' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:195]
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WARNING: [Synth 8-7023] instance 'u_upload_protocol_ql' of module 'upload_protocol_ql' has 25 connections declared, but only 24 given [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:195]
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INFO: [Synth 8-6157] synthesizing module 'upload_protocol_intan' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_protocol_intan' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'upload_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:3]
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WARNING: [Synth 8-7071] port 'interrupt' of module 'upload_top' is unconnected for instance 'u_upload_top' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v:377]
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WARNING: [Synth 8-7023] instance 'u_upload_top' of module 'upload_top' has 33 connections declared, but only 32 given [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v:377]
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INFO: [Synth 8-6155] done synthesizing module 'pl_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'led_ctrl' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/led_ctrl.v:3]
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|
Parameter CLK_PERIOD bound to: 10 - type: integer
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|
INFO: [Synth 8-6157] synthesizing module 'pwm_gen' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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|
Parameter DATA_WIDTH bound to: 28 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'pwm_gen' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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INFO: [Synth 8-6157] synthesizing module 'breath_gen' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v:3]
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|
Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'pwm_gen__parameterized0' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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|
Parameter DATA_WIDTH bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'pwm_gen__parameterized0' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'breath_gen' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'led_ctrl' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/led_ctrl.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'c64pro_top' (0#1) [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/c64pro_top.v:3]
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WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:170]
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|
WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:181]
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|
WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:192]
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|
WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:207]
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WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:223]
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|
WARNING: [Synth 8-6014] Unused sequential element unknow_data_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v:270]
|
|
WARNING: [Synth 8-6014] Unused sequential element rx_data[0].cnv_res_tlast_r_reg[0] was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:94]
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|
WARNING: [Synth 8-6014] Unused sequential element rx_data[1].cnv_res_tlast_r_reg[1] was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:94]
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WARNING: [Synth 8-6014] Unused sequential element rx_data[2].cnv_res_tlast_r_reg[2] was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:94]
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|
WARNING: [Synth 8-6014] Unused sequential element rx_data[3].cnv_res_tlast_r_reg[3] was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v:94]
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|
WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:94]
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|
WARNING: [Synth 8-3848] Net eeg_sr in module/entity eeg_top does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:55]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_protocol_ql does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:14]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_protocol_intan does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:13]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_top does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:21]
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|
WARNING: [Synth 8-3848] Net s_axis_emg_tready in module/entity upload_top does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:39]
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WARNING: [Synth 8-3848] Net debug_sig in module/entity upload_top does not have driver. [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:51]
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|
WARNING: [Synth 8-3917] design c64pro_top has port led_pl[1] driven by constant 0
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|
WARNING: [Synth 8-3917] design c64pro_top has port led_pl[0] driven by constant 0
|
|
WARNING: [Synth 8-7129] Port interrupt in module upload_protocol_intan is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port interrupt in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[215] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[214] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[213] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[212] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[211] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[210] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[209] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[208] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[207] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[206] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[205] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[204] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[203] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[202] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[201] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[200] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[199] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[198] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[197] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[196] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[195] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[194] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[193] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[192] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[191] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[190] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[189] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[188] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[187] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[186] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[185] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[184] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[175] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[174] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[173] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[172] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[171] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[170] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[169] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[168] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[167] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[166] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[165] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[164] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[163] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[162] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[161] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[160] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[159] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[158] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[157] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[156] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[155] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[154] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[153] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[152] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[151] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[150] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[149] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[148] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[147] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[146] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[145] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[144] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[143] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[142] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[141] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[140] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[139] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[138] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[137] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[136] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[135] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[134] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[133] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[132] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[131] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[130] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[129] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[128] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[127] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[126] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[125] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[124] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[123] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[122] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[121] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[120] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[119] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[118] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[117] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[116] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[115] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[114] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[113] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[112] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port accel_data[47] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port accel_data[46] in module upload_protocol_ql is either unconnected or has no load
|
|
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2655.008 ; gain = 773.887
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2672.938 ; gain = 791.816
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2672.938 ; gain = 791.816
|
|
---------------------------------------------------------------------------------
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.282 . Memory (MB): peak = 2685.008 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
|
|
Processing XDC Constraints
|
|
Initializing timing engine
|
|
Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/u_mult_gain'
|
|
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/u_mult_gain'
|
|
Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/u_mult_gain'
|
|
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/u_mult_gain'
|
|
Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/u_mult_gain'
|
|
Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/u_mult_gain'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/u_mult_gain'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8/mult_gen_au8_bu9_p8_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/u_mult_gain'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0/design_a9_1_axi_iic_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_1'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_1_0/design_a9_1_axi_iic_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_iic_1'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch/dds_stim_16ch_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch/dds_stim_16ch_in_context.xdc] for cell 'u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_in_context.xdc] for cell 'u_pl_top/u_trigger_top/u_trigger_fifo'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16/axis_data_fifo_w32_d16_in_context.xdc] for cell 'u_pl_top/u_trigger_top/u_trigger_fifo'
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Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Finished Parsing XDC File [d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_misc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_pm.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/constrs_1/new/c64pro_pins_rsh2116.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/dont_touch.xdc]
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Finished Parsing XDC File [D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/dont_touch.xdc]
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Completed Processing XDC Constraints
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2787.656 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 4 instances were transformed.
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IOBUF => IOBUF (IBUF, OBUFT): 4 instances
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.102 . Memory (MB): peak = 2787.656 ; gain = 0.000
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WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/u_mult_gain' at clock pin 'CLK' is different from the actual clock period '10.000', this can lead to different synthesis results.
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WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/u_mult_gain' at clock pin 'CLK' is different from the actual clock period '10.000', this can lead to different synthesis results.
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WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/u_mult_gain' at clock pin 'CLK' is different from the actual clock period '10.000', this can lead to different synthesis results.
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WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/u_mult_gain' at clock pin 'CLK' is different from the actual clock period '10.000', this can lead to different synthesis results.
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2787.672 ; gain = 906.551
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7z010clg400-2
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2787.672 ; gain = 906.551
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 2).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 3).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 4).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 5).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 6).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 7).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 8).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 9).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 10).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 11).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 12).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 13).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 14).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 15).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 16).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 17).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 18).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 19).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 20).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 21).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 22).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 23).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 24).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 25).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 26).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 27).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 28).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 29).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 30).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 31).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 32).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 33).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 34).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 35).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 36).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 37).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 38).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 39).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 40).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 41).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 42).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 43).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 44).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 45).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 46).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 47).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 48).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 49).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 50).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 51).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 52).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 53).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 54).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 55).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 56).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 57).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 58).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 59).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 60).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 61).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 62).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 63).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 64).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 65).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 66).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 67).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 68).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 69).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 70).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 71).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 72).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 73).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 74).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 75).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 76).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 77).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 78).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 79).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 80).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 81).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 82).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 83).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 84).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 85).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 86).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 87).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 88).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 89).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 90).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 91).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 92).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 93).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 94).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 95).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 96).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 97).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 98).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 99).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 100).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 101).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 102).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 103).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 104).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 105).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 106).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 107).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 108).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 109).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 110).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 111).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 112).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 113).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 114).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 115).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 116).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 117).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 118).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 119).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 120).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 121).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 122).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 123).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 124).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 125).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 126).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 127).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 128).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 129).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 130).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 131).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 132).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 133).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 134).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 135).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 136).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 137).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 138).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 139).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 140).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 141).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 142).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 143).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 144).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 145).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 146).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 147).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 148).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 149).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 150).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 151).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 152).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 153).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 154).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 155).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 156).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 157).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 158).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 159).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 160).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 161).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 162).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 163).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 164).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 165).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 166).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 167).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 168).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 169).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 170).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 171).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 172).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 173).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 174).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 175).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 176).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 177).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 178).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 179).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 180).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 181).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 182).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 183).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 184).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 185).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 186).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 187).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 188).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 189).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 190).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 191).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 192).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 193).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 194).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 195).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 196).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 197).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 198).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 199).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 200).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 201).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 202).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 203).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 204).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 205).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 206).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 207).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 208).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 209).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 210).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 211).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 212).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 213).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 214).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 215).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 216).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 217).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 218).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 219).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 220).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 221).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 222).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 223).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 224).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 225).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 226).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 227).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 228).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 229).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 230).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 231).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 232).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 233).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 234).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 235).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 236).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 237).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 238).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 239).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 240).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 241).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 242).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 243).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 244).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 245).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 246).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 247).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 248).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 249).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 250).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 251).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 252).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 253).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 254).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 255).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 256).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 257).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 258).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 259).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 260).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/projects/vivadoPrj/c64_pro/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 261).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/\transmit_arrange[0].u_trans_arrange /u_mult_gain. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/\transmit_arrange[1].u_trans_arrange /u_mult_gain. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/\transmit_arrange[2].u_trans_arrange /u_mult_gain. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/\transmit_arrange[3].u_trans_arrange /u_mult_gain. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/processing_system7_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_iic_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_gpio_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/xlconcat_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_smc. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/smartconnect_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_iic_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/u_trans_distribute/\output_fifo[0].u_axis_data_fifo_if_recv . (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/u_trans_distribute/\output_fifo[1].u_axis_data_fifo_if_recv . (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/u_trans_distribute/\output_fifo[2].u_axis_data_fifo_if_recv . (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/u_trans_distribute/\output_fifo[3].u_axis_data_fifo_if_recv . (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_trigger_top/u_trigger_fifo. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128. (constraint file auto generated constraint).
|
|
---------------------------------------------------------------------------------
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'debouncing'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'trans_arrange__xdcDup__1'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'trans_arrange__xdcDup__2'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'trans_arrange__xdcDup__3'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'trans_arrange'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'spi_full_duplex_master'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'sine_gen'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'trans_distribute'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'cnv_res_collect'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ads1299_arrange'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ads1299_spi'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'eeg_upload'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'adg1414_if'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'channel_switch'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_sort'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_protocol_ql'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_protocol_intan'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'breath_gen'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 00 | 0000
|
|
DELAY1_ST | 01 | 0001
|
|
DELAY2_ST | 10 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'debouncing'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
RX_ST | 000 | 0000
|
|
DECODE_ST | 100 | 0001
|
|
FILL_ST | 011 | 0010
|
|
POL_ST | 010 | 0011
|
|
SEND_ST | 001 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'trans_arrange__xdcDup__1'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
RX_ST | 000 | 0000
|
|
DECODE_ST | 100 | 0001
|
|
FILL_ST | 011 | 0010
|
|
POL_ST | 010 | 0011
|
|
SEND_ST | 001 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'trans_arrange__xdcDup__2'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
RX_ST | 000 | 0000
|
|
DECODE_ST | 100 | 0001
|
|
FILL_ST | 011 | 0010
|
|
POL_ST | 010 | 0011
|
|
SEND_ST | 001 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'trans_arrange__xdcDup__3'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
RX_ST | 000 | 0000
|
|
DECODE_ST | 100 | 0001
|
|
FILL_ST | 011 | 0010
|
|
POL_ST | 010 | 0011
|
|
SEND_ST | 001 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'trans_arrange'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
TRANS_ST | 010 | 0001
|
|
END_ST | 100 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'spi_full_duplex_master'
|
|
WARNING: [Synth 8-327] inferring latch for variable 'spi_din_r_reg' [D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v:311]
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0 | 0000
|
|
TRANS_ST | 1 | 0001
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'sine_gen'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0 | 0000
|
|
TX_ST | 1 | 0001
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'trans_distribute'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0 | 0000
|
|
SCAN_ST | 1 | 0001
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'cnv_res_collect'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 000 | 0000
|
|
TRANS_ST | 101 | 0001
|
|
WAIT_ST | 100 | 0010
|
|
RDATAC_ST | 010 | 0011
|
|
REVC_1_ST | 011 | 0100
|
|
REVC_2_ST | 001 | 0101
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'ads1299_arrange'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0001 | 0000
|
|
TRANS_ST | 1000 | 0001
|
|
SCCS_ST | 0100 | 0010
|
|
CSH_ST | 0010 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'ads1299_spi'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
READY_ST | 100 | 0001
|
|
SCAN_ST | 010 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'eeg_upload'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 00 | 0000
|
|
TRANS_ST | 10 | 0001
|
|
END_ST | 01 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'adg1414_if'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
MON_ST | 010 | 0001
|
|
CFG_ST | 100 | 1011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'channel_switch'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 0001 | 0000
|
|
ST_RX | 0010 | 0001
|
|
ST_SCAN | 0100 | 0010
|
|
ST_TX | 1000 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'upload_sort'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 000 | 0000
|
|
ST_MSG_HEAD | 111 | 0001
|
|
ST_WAIT | 010 | 0010
|
|
ST_MSG_CRC | 011 | 0110
|
|
ST_ADDITIONAL | 001 | 0111
|
|
ST_READ_TRIGGER | 110 | 0011
|
|
ST_MSG_TRIGGER | 101 | 0100
|
|
ST_MSG_RECORD | 100 | 0101
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'upload_protocol_ql'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 000000010000 | 0000
|
|
ST_MSG_HEAD | 000000001000 | 0010
|
|
ST_MSG_DATA_H | 000000000001 | 0011
|
|
ST_MSG_RECORD | 000000000010 | 0100
|
|
ST_MSG_DATA_T | 000000000100 | 0101
|
|
ST_MSG_REG_VAL | 100000000000 | 0110
|
|
ST_MSG_DA_AD | 000100000000 | 0111
|
|
ST_MSG_TRIG_IN | 001000000000 | 1000
|
|
ST_MSG_TRIG_OUT | 010000000000 | 1001
|
|
ST_WAIT | 000001000000 | 0001
|
|
ST_MSG_CRC | 000010000000 | 1010
|
|
ST_ADDITIONAL | 000000100000 | 1011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'upload_protocol_intan'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 000 | 0000
|
|
UP_ST | 001 | 0001
|
|
PEAK_ST | 010 | 0010
|
|
DOWN_ST | 011 | 0011
|
|
REST_ST | 100 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'breath_gen'
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 32 Bit Adders := 13
|
|
2 Input 28 Bit Adders := 2
|
|
2 Input 20 Bit Adders := 2
|
|
2 Input 16 Bit Adders := 10
|
|
2 Input 12 Bit Adders := 1
|
|
2 Input 10 Bit Adders := 4
|
|
2 Input 9 Bit Adders := 9
|
|
2 Input 8 Bit Adders := 65
|
|
2 Input 6 Bit Adders := 3
|
|
2 Input 4 Bit Adders := 11
|
|
2 Input 3 Bit Adders := 1
|
|
2 Input 2 Bit Adders := 1
|
|
+---XORs :
|
|
2 Input 1 Bit XORs := 20
|
|
6 Input 1 Bit XORs := 2
|
|
4 Input 1 Bit XORs := 4
|
|
7 Input 1 Bit XORs := 2
|
|
3 Input 1 Bit XORs := 12
|
|
5 Input 1 Bit XORs := 2
|
|
+---Registers :
|
|
64 Bit Registers := 9
|
|
32 Bit Registers := 205
|
|
28 Bit Registers := 3
|
|
20 Bit Registers := 2
|
|
16 Bit Registers := 24
|
|
12 Bit Registers := 1
|
|
9 Bit Registers := 40
|
|
8 Bit Registers := 418
|
|
6 Bit Registers := 12
|
|
5 Bit Registers := 1
|
|
4 Bit Registers := 19
|
|
2 Bit Registers := 9
|
|
1 Bit Registers := 250
|
|
+---Muxes :
|
|
2 Input 64 Bit Muxes := 4
|
|
9 Input 64 Bit Muxes := 1
|
|
2 Input 32 Bit Muxes := 62
|
|
4 Input 32 Bit Muxes := 9
|
|
13 Input 32 Bit Muxes := 1
|
|
3 Input 32 Bit Muxes := 1
|
|
2 Input 28 Bit Muxes := 4
|
|
2 Input 20 Bit Muxes := 2
|
|
2 Input 16 Bit Muxes := 16
|
|
12 Input 12 Bit Muxes := 1
|
|
2 Input 12 Bit Muxes := 15
|
|
2 Input 9 Bit Muxes := 48
|
|
2 Input 8 Bit Muxes := 573
|
|
4 Input 8 Bit Muxes := 6
|
|
3 Input 8 Bit Muxes := 6
|
|
7 Input 8 Bit Muxes := 1
|
|
2 Input 6 Bit Muxes := 1
|
|
2 Input 4 Bit Muxes := 54
|
|
4 Input 4 Bit Muxes := 5
|
|
8 Input 4 Bit Muxes := 1
|
|
12 Input 4 Bit Muxes := 7
|
|
13 Input 4 Bit Muxes := 1
|
|
5 Input 4 Bit Muxes := 1
|
|
2 Input 3 Bit Muxes := 113
|
|
8 Input 3 Bit Muxes := 6
|
|
3 Input 3 Bit Muxes := 30
|
|
6 Input 3 Bit Muxes := 20
|
|
5 Input 3 Bit Muxes := 13
|
|
12 Input 3 Bit Muxes := 1
|
|
3 Input 2 Bit Muxes := 39
|
|
2 Input 2 Bit Muxes := 91
|
|
4 Input 2 Bit Muxes := 23
|
|
2 Input 1 Bit Muxes := 467
|
|
3 Input 1 Bit Muxes := 18
|
|
5 Input 1 Bit Muxes := 128
|
|
7 Input 1 Bit Muxes := 2
|
|
4 Input 1 Bit Muxes := 6
|
|
8 Input 1 Bit Muxes := 5
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 80 (col length:40)
|
|
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
|
WARNING: [Synth 8-3917] design c64pro_top has port led_pl[1] driven by constant 0
|
|
WARNING: [Synth 8-3917] design c64pro_top has port led_pl[0] driven by constant 0
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:10 ; elapsed = 00:01:23 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
ROM: Preliminary Mapping Report
|
|
+------------+--------------+---------------+----------------+
|
|
|Module Name | RTL Object | Depth x Width | Implemented As |
|
|
+------------+--------------+---------------+----------------+
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
+------------+--------------+---------------+----------------+
|
|
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:15 ; elapsed = 00:01:29 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:32 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:01:24 ; elapsed = 00:01:38 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:01:28 ; elapsed = 00:01:43 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:01:28 ; elapsed = 00:01:43 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:44 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:44 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:45 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:01:30 ; elapsed = 00:01:45 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+------+-----------------------------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+------+-----------------------------------+----------+
|
|
|1 |mult_gen_au8_bu9_p8 | 4|
|
|
|2 |dds_stim_16ch | 1|
|
|
|3 |axis_data_fifo_w32_d32 | 4|
|
|
|4 |axis_data_fifo_w32_d16 | 1|
|
|
|5 |axis_data_fifo_w8_d128 | 1|
|
|
|6 |design_a9_1_axi_bram_ctrl_0_0 | 1|
|
|
|7 |design_a9_1_axi_bram_ctrl_1_0 | 1|
|
|
|8 |design_a9_1_axi_bram_ctrl_2_0 | 1|
|
|
|9 |design_a9_1_axi_bram_ctrl_3_0 | 1|
|
|
|10 |design_a9_1_axi_bram_ctrl_4_0 | 1|
|
|
|11 |design_a9_1_axi_dma_0_0 | 1|
|
|
|12 |design_a9_1_axi_dma_1_0 | 1|
|
|
|13 |design_a9_1_axi_gpio_0_0 | 1|
|
|
|14 |design_a9_1_axi_iic_0_0 | 1|
|
|
|15 |design_a9_1_axi_iic_1_0 | 1|
|
|
|16 |design_a9_1_axi_smc_0 | 1|
|
|
|17 |design_a9_1_axis_data_fifo_0_0 | 1|
|
|
|18 |design_a9_1_axis_data_fifo_1_0 | 1|
|
|
|19 |design_a9_1_processing_system7_0_0 | 1|
|
|
|20 |design_a9_1_rst_ps7_0_50M_0 | 1|
|
|
|21 |design_a9_1_smartconnect_0_0 | 1|
|
|
+------+-----------------------------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+---------------------------------+------+
|
|
| |Cell |Count |
|
|
+------+---------------------------------+------+
|
|
|1 |axis_data_fifo_w32_d16 | 1|
|
|
|2 |axis_data_fifo_w32_d32 | 4|
|
|
|6 |axis_data_fifo_w8_d128 | 1|
|
|
|7 |dds_stim_16ch | 1|
|
|
|8 |design_a9_1_axi_bram_ctrl_0 | 1|
|
|
|9 |design_a9_1_axi_bram_ctrl_1 | 1|
|
|
|10 |design_a9_1_axi_bram_ctrl_2 | 1|
|
|
|11 |design_a9_1_axi_bram_ctrl_3 | 1|
|
|
|12 |design_a9_1_axi_bram_ctrl_4 | 1|
|
|
|13 |design_a9_1_axi_dma_0 | 1|
|
|
|14 |design_a9_1_axi_dma_1 | 1|
|
|
|15 |design_a9_1_axi_gpio_0 | 1|
|
|
|16 |design_a9_1_axi_iic_0 | 1|
|
|
|17 |design_a9_1_axi_iic_1 | 1|
|
|
|18 |design_a9_1_axi_smc | 1|
|
|
|19 |design_a9_1_axis_data_fifo_0 | 1|
|
|
|20 |design_a9_1_axis_data_fifo_1 | 1|
|
|
|21 |design_a9_1_processing_system7_0 | 1|
|
|
|22 |design_a9_1_rst_ps7_0_50M | 1|
|
|
|23 |design_a9_1_smartconnect_0 | 1|
|
|
|24 |mult_gen_au8_bu9_p8 | 4|
|
|
|28 |BUFG | 4|
|
|
|29 |CARRY4 | 274|
|
|
|30 |LUT1 | 133|
|
|
|31 |LUT2 | 841|
|
|
|32 |LUT3 | 855|
|
|
|33 |LUT4 | 672|
|
|
|34 |LUT5 | 846|
|
|
|35 |LUT6 | 3858|
|
|
|36 |MUXF7 | 997|
|
|
|37 |MUXF8 | 452|
|
|
|38 |FDCE | 10710|
|
|
|39 |FDPE | 366|
|
|
|40 |FDSE | 32|
|
|
|41 |LDC | 128|
|
|
|42 |IBUF | 16|
|
|
|43 |IOBUF | 4|
|
|
|44 |OBUF | 56|
|
|
+------+---------------------------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:01:30 ; elapsed = 00:01:45 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:01:17 ; elapsed = 00:01:39 . Memory (MB): peak = 2787.672 ; gain = 791.816
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:01:30 ; elapsed = 00:01:45 . Memory (MB): peak = 2787.672 ; gain = 906.551
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 2787.672 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 1855 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2787.672 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 132 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 4 instances
|
|
LDC => LDCE: 128 instances
|
|
|
|
Synth Design complete | Checksum: 91bc6ad0
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
183 Infos, 169 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:01:35 ; elapsed = 00:02:02 . Memory (MB): peak = 2787.672 ; gain = 1316.754
|
|
INFO: [Common 17-1381] The checkpoint 'D:/projects/vivadoPrj/c64_pro/c64_pro.runs/synth_1/c64pro_top.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Aug 4 13:40:31 2024...
|