117 lines
2.9 KiB
Verilog
117 lines
2.9 KiB
Verilog
`timescale 1 ns / 1 ps
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module trans_timer#
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(
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parameter CLK_PERIOD = 20 ,
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parameter START_DELAY_NS = 100000,
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parameter SPI_TRANS_PERIOD = 1500
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)
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(
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input clk ,
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input rst_n ,
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input [32-1:0] update_period ,
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input enable ,
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output trans_round ,
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output trans_pulse
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam T_START_DLY = START_DELAY_NS/CLK_PERIOD-1 ;
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localparam T_TRANS = SPI_TRANS_PERIOD/CLK_PERIOD ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] start_clocks_cnt ;
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reg [32-1:0] stop_clocks_cnt ;
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reg start ;
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reg [32-1:0] update_clocks_cnt ;
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reg update_r ;
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reg [ 8-1:0] clk_cnt ;
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reg trans_r ;
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//*****************************************************************************
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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start_clocks_cnt <= 0;
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else if ( enable && start_clocks_cnt != T_START_DLY )
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start_clocks_cnt <= start_clocks_cnt + 1'b1;
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else if ( ~enable )
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start_clocks_cnt <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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stop_clocks_cnt <= 0;
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else if ( enable )
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stop_clocks_cnt <= 0;
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else
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stop_clocks_cnt <= stop_clocks_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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start <= 1'b0;
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else if ( start_clocks_cnt == T_START_DLY )
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start <= 1'b1;
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else if ( stop_clocks_cnt == update_period )
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start <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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update_clocks_cnt <= 0;
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else if ( ~start )
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update_clocks_cnt <= 0;
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else if ( update_clocks_cnt == update_period - 1 )
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update_clocks_cnt <= 0;
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else
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update_clocks_cnt <= update_clocks_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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update_r <= 0;
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else if ( start && update_clocks_cnt == 0 )
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update_r <= 1;
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else
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update_r <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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clk_cnt <= 0;
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else if ( ~start )
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clk_cnt <= 0;
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else if ( update_clocks_cnt == update_period - 1 )
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clk_cnt <= 0;
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else if ( clk_cnt == T_TRANS-1 )
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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trans_r <= 0;
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else if ( clk_cnt == T_TRANS-1 )
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trans_r <= 1;
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else
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trans_r <= 0;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign trans_round = update_r;
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assign trans_pulse = trans_r;
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endmodule
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