GEM/BSI-901-fpga-software
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BSI-901-fpga-software/c64_pro.runs/impl_1/c64pro_top_timing_summary_routed.rpt
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chenmin 25cdd3c44c 上传PL工程
2024-10-28 13:14:49 +08:00

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Sun Aug 4 13:44:40 2024
| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file c64pro_top_timing_summary_routed.rpt -pb c64pro_top_timing_summary_routed.pb -rpx c64pro_top_timing_summary_routed.rpx -warn_on_violation
| Design : c64pro_top
| Device : 7z010-clg400
| Speed File : -2 PRODUCTION 1.12 2019-11-22
| Design State : Routed
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
Rule Severity Description Violations
--------- -------- ----------------------------------------- ----------
TIMING-18 Warning Missing input or output delay 72
TIMING-20 Warning Non-clocked latch 128
ULMTCS-2 Warning Control Sets use limits require reduction 1
LATCH-1 Advisory Existing latches in the design 1
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
check_timing report
Table of Contents
-----------------
1. checking no_clock (256)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (256)
5. checking no_input_delay (20)
6. checking no_output_delay (49)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (256)
--------------------------
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/spi_cmd_ready_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/trans_data_en_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/spi_cmd_ready_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/trans_data_en_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/spi_cmd_ready_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/trans_data_en_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/spi_cmd_ready_reg/Q (HIGH)
There are 32 register/latch pins with no clock driven by root clock pin: u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/trans_data_en_reg/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (256)
--------------------------------------------------
There are 256 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (20)
-------------------------------
There are 20 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (49)
--------------------------------
There are 49 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.129 0.000 0 56891 0.036 0.000 0 56891 3.870 0.000 0 19789
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_fpga_0 {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk_fpga_0 0.129 0.000 0 45812 0.036 0.000 0 45812 3.870 0.000 0 19789
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** clk_fpga_0 clk_fpga_0 1.084 0.000 0 11079 1.187 0.000 0 11079
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 0.129ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.129ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][10]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.355ns (logic 1.873ns (20.022%) route 7.482ns (79.978%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.194ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.245ns = ( 12.245 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.730 11.895 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][10]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.253 12.245 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][10]/C
clock pessimism 0.101 12.346
clock uncertainty -0.154 12.192
SLICE_X35Y14 FDCE (Setup_fdce_C_CE) -0.168 12.024 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][10]
-------------------------------------------------------------------
required time 12.024
arrival time -11.895
-------------------------------------------------------------------
slack 0.129
Slack (MET) : 0.129ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][11]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.355ns (logic 1.873ns (20.022%) route 7.482ns (79.978%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.194ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.245ns = ( 12.245 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.730 11.895 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][11]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.253 12.245 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][11]/C
clock pessimism 0.101 12.346
clock uncertainty -0.154 12.192
SLICE_X35Y14 FDCE (Setup_fdce_C_CE) -0.168 12.024 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][11]
-------------------------------------------------------------------
required time 12.024
arrival time -11.895
-------------------------------------------------------------------
slack 0.129
Slack (MET) : 0.129ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][6]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.355ns (logic 1.873ns (20.022%) route 7.482ns (79.978%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.194ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.245ns = ( 12.245 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.730 11.895 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][6]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.253 12.245 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][6]/C
clock pessimism 0.101 12.346
clock uncertainty -0.154 12.192
SLICE_X35Y14 FDCE (Setup_fdce_C_CE) -0.168 12.024 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][6]
-------------------------------------------------------------------
required time 12.024
arrival time -11.895
-------------------------------------------------------------------
slack 0.129
Slack (MET) : 0.129ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][7]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.355ns (logic 1.873ns (20.022%) route 7.482ns (79.978%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.194ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.245ns = ( 12.245 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.730 11.895 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][7]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.253 12.245 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][7]/C
clock pessimism 0.101 12.346
clock uncertainty -0.154 12.192
SLICE_X35Y14 FDCE (Setup_fdce_C_CE) -0.168 12.024 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][7]
-------------------------------------------------------------------
required time 12.024
arrival time -11.895
-------------------------------------------------------------------
slack 0.129
Slack (MET) : 0.129ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][8]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.355ns (logic 1.873ns (20.022%) route 7.482ns (79.978%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.194ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.245ns = ( 12.245 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.730 11.895 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][8]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.253 12.245 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X35Y14 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][8]/C
clock pessimism 0.101 12.346
clock uncertainty -0.154 12.192
SLICE_X35Y14 FDCE (Setup_fdce_C_CE) -0.168 12.024 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][8]
-------------------------------------------------------------------
required time 12.024
arrival time -11.895
-------------------------------------------------------------------
slack 0.129
Slack (MET) : 0.198ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][0]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.275ns (logic 1.873ns (20.193%) route 7.402ns (79.807%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.204ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.235ns = ( 12.235 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.650 11.815 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][0]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.243 12.235 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][0]/C
clock pessimism 0.101 12.336
clock uncertainty -0.154 12.182
SLICE_X27Y22 FDCE (Setup_fdce_C_CE) -0.168 12.014 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][0]
-------------------------------------------------------------------
required time 12.014
arrival time -11.815
-------------------------------------------------------------------
slack 0.198
Slack (MET) : 0.198ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][16]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.275ns (logic 1.873ns (20.193%) route 7.402ns (79.807%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.204ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.235ns = ( 12.235 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.650 11.815 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][16]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.243 12.235 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][16]/C
clock pessimism 0.101 12.336
clock uncertainty -0.154 12.182
SLICE_X27Y22 FDCE (Setup_fdce_C_CE) -0.168 12.014 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][16]
-------------------------------------------------------------------
required time 12.014
arrival time -11.815
-------------------------------------------------------------------
slack 0.198
Slack (MET) : 0.198ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][1]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.275ns (logic 1.873ns (20.193%) route 7.402ns (79.807%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.204ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.235ns = ( 12.235 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.650 11.815 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][1]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.243 12.235 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][1]/C
clock pessimism 0.101 12.336
clock uncertainty -0.154 12.182
SLICE_X27Y22 FDCE (Setup_fdce_C_CE) -0.168 12.014 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][1]
-------------------------------------------------------------------
required time 12.014
arrival time -11.815
-------------------------------------------------------------------
slack 0.198
Slack (MET) : 0.198ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][20]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.275ns (logic 1.873ns (20.193%) route 7.402ns (79.807%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.204ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.235ns = ( 12.235 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.650 11.815 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][20]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.243 12.235 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][20]/C
clock pessimism 0.101 12.336
clock uncertainty -0.154 12.182
SLICE_X27Y22 FDCE (Setup_fdce_C_CE) -0.168 12.014 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][20]
-------------------------------------------------------------------
required time 12.014
arrival time -11.815
-------------------------------------------------------------------
slack 0.198
Slack (MET) : 0.198ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][26]/CE
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 9.275ns (logic 1.873ns (20.193%) route 7.402ns (79.807%))
Logic Levels: 9 (LUT2=4 LUT5=2 LUT6=3)
Clock Path Skew: -0.204ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.235ns = ( 12.235 - 10.000 )
Source Clock Delay (SCD): 2.540ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.447 2.540 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/s_sc_aclk
SLICE_X5Y54 FDRE r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/C
------------------------------------------------------------------- -------------------
SLICE_X5Y54 FDRE (Prop_fdre_C_Q) 0.379 2.919 f u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.empty_r_reg/Q
net (fo=16, routed) 0.953 3.872 u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/empty_r
SLICE_X10Y55 LUT2 (Prop_lut2_I1_O) 0.105 3.977 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.337 4.314 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/s_sc_send[0]
SLICE_X10Y55 LUT2 (Prop_lut2_I0_O) 0.105 4.419 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_send[0]_INST_0/O
net (fo=1, routed) 0.460 4.879 u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/s_axi_wvalid
SLICE_X9Y54 LUT2 (Prop_lut2_I0_O) 0.105 4.984 r u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/m_axi_wvalid_INST_0/O
net (fo=1, routed) 0.459 5.443 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_wvalid
SLICE_X9Y50 LUT6 (Prop_lut6_I5_O) 0.105 5.548 f u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1/O
net (fo=12, routed) 0.688 6.235 u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0_i_1_n_0
SLICE_X10Y47 LUT5 (Prop_lut5_I3_O) 0.125 6.360 r u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/bram_en_a_INST_0/O
net (fo=7, routed) 1.194 7.554 u_ps_a9_1/bram_stim_en
SLICE_X16Y45 LUT5 (Prop_lut5_I0_O) 0.275 7.829 f u_ps_a9_1/enable_timer_i_2/O
net (fo=14, routed) 0.745 8.574 u_ps_a9_1/enable_timer_i_2_n_4
SLICE_X29Y43 LUT6 (Prop_lut6_I0_O) 0.283 8.857 r u_ps_a9_1/dds_phase_off[0][31]_i_2/O
net (fo=11, routed) 1.131 9.988 u_ps_a9_1/dds_phase_off[0][31]_i_2_n_4
SLICE_X31Y28 LUT2 (Prop_lut2_I0_O) 0.124 10.112 r u_ps_a9_1/dds_phase_off[4][31]_i_2/O
net (fo=6, routed) 0.787 10.898 u_ps_a9_1/dds_phase_off[4][31]_i_2_n_4
SLICE_X30Y18 LUT6 (Prop_lut6_I0_O) 0.267 11.165 r u_ps_a9_1/dds_phase_off[8][31]_i_1/O
net (fo=32, routed) 0.650 11.815 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][31]_0[0]
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][26]/CE
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.243 12.235 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X27Y22 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][26]/C
clock pessimism 0.101 12.336
clock uncertainty -0.154 12.182
SLICE_X27Y22 FDCE (Setup_fdce_C_CE) -0.168 12.014 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[8][26]
-------------------------------------------------------------------
required time 12.014
arrival time -11.815
-------------------------------------------------------------------
slack 0.198
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.036ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1056]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA/I
(rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%))
Logic Levels: 0
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.211ns
Source Clock Delay (SCD): 0.916ns
Clock Pessimism Removal (CPR): 0.282ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.575 0.916 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/aclk
SLICE_X1Y19 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1056]/C
------------------------------------------------------------------- -------------------
SLICE_X1Y19 FDRE (Prop_fdre_C_Q) 0.141 1.057 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1056]/Q
net (fo=1, routed) 0.055 1.112 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/DIA0
SLICE_X0Y19 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA/I
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.841 1.211 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/WCLK
SLICE_X0Y19 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA/CLK
clock pessimism -0.282 0.929
SLICE_X0Y19 RAMD32 (Hold_ramd32_CLK_I)
0.147 1.076 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA
-------------------------------------------------------------------
required time -1.076
arrival time 1.112
-------------------------------------------------------------------
slack 0.036
Slack (MET) : 0.044ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][98]/D
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.331ns (logic 0.148ns (44.656%) route 0.183ns (55.344%))
Logic Levels: 0
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.201ns
Source Clock Delay (SCD): 0.902ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.561 0.902 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
SLICE_X24Y2 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]/C
------------------------------------------------------------------- -------------------
SLICE_X24Y2 FDRE (Prop_fdre_C_Q) 0.148 1.049 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]/Q
net (fo=1, routed) 0.183 1.233 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[31]
SLICE_X21Y0 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][98]/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.831 1.201 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
SLICE_X21Y0 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][98]/C
clock pessimism -0.034 1.167
SLICE_X21Y0 FDRE (Hold_fdre_C_D) 0.022 1.189 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][98]
-------------------------------------------------------------------
required time -1.189
arrival time 1.233
-------------------------------------------------------------------
slack 0.044
Slack (MET) : 0.045ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[19]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4/D
(rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.244ns (logic 0.141ns (57.816%) route 0.103ns (42.184%))
Logic Levels: 0
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.197ns
Source Clock Delay (SCD): 0.900ns
Clock Pessimism Removal (CPR): 0.281ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.559 0.900 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
SLICE_X22Y8 FDRE r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[19]/C
------------------------------------------------------------------- -------------------
SLICE_X22Y8 FDRE (Prop_fdre_C_Q) 0.141 1.041 r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[19]/Q
net (fo=1, routed) 0.103 1.143 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[19]
SLICE_X24Y7 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.827 1.197 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
SLICE_X24Y7 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4/CLK
clock pessimism -0.281 0.916
SLICE_X24Y7 SRL16E (Hold_srl16e_CLK_D)
0.183 1.099 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4
-------------------------------------------------------------------
required time -1.099
arrival time 1.143
-------------------------------------------------------------------
slack 0.045
Slack (MET) : 0.055ns (arrival time - required time)
Source: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[30]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[11]
(rising edge-triggered cell RAMB18E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.287ns (logic 0.141ns (49.087%) route 0.146ns (50.913%))
Logic Levels: 0
Clock Path Skew: 0.050ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.226ns
Source Clock Delay (SCD): 0.894ns
Clock Pessimism Removal (CPR): 0.282ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.553 0.894 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/aclk
SLICE_X35Y22 FDRE r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[30]/C
------------------------------------------------------------------- -------------------
SLICE_X35Y22 FDRE (Prop_fdre_C_Q) 0.141 1.035 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[30]/Q
net (fo=1, routed) 0.146 1.181 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/D[7]
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[11]
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.856 1.226 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/CLKARDCLK
clock pessimism -0.282 0.943
RAMB18_X2Y8 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11])
0.183 1.126 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg
-------------------------------------------------------------------
required time -1.126
arrival time 1.181
-------------------------------------------------------------------
slack 0.055
Slack (MET) : 0.055ns (arrival time - required time)
Source: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[31]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[12]
(rising edge-triggered cell RAMB18E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.287ns (logic 0.141ns (49.087%) route 0.146ns (50.913%))
Logic Levels: 0
Clock Path Skew: 0.050ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.226ns
Source Clock Delay (SCD): 0.894ns
Clock Pessimism Removal (CPR): 0.282ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.553 0.894 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/aclk
SLICE_X35Y22 FDRE r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[31]/C
------------------------------------------------------------------- -------------------
SLICE_X35Y22 FDRE (Prop_fdre_C_Q) 0.141 1.035 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[31]/Q
net (fo=1, routed) 0.146 1.181 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/D[8]
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[12]
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.856 1.226 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/CLKARDCLK
clock pessimism -0.282 0.943
RAMB18_X2Y8 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[12])
0.183 1.126 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg
-------------------------------------------------------------------
required time -1.126
arrival time 1.181
-------------------------------------------------------------------
slack 0.055
Slack (MET) : 0.056ns (arrival time - required time)
Source: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[28]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[9]
(rising edge-triggered cell RAMB18E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.289ns (logic 0.141ns (48.798%) route 0.148ns (51.202%))
Logic Levels: 0
Clock Path Skew: 0.050ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.226ns
Source Clock Delay (SCD): 0.894ns
Clock Pessimism Removal (CPR): 0.282ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.553 0.894 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/aclk
SLICE_X35Y22 FDRE r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[28]/C
------------------------------------------------------------------- -------------------
SLICE_X35Y22 FDRE (Prop_fdre_C_Q) 0.141 1.035 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_fabric.i_ph_adj_pipe/opt_has_pipe.first_q_reg[28]/Q
net (fo=1, routed) 0.148 1.182 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/D[5]
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ADDRARDADDR[9]
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.856 1.226 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
RAMB18_X2Y8 RAMB18E1 r u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/CLKARDCLK
clock pessimism -0.282 0.943
RAMB18_X2Y8 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[9])
0.183 1.126 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg
-------------------------------------------------------------------
required time -1.126
arrival time 1.182
-------------------------------------------------------------------
slack 0.056
Slack (MET) : 0.060ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][120]/D
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.343ns (logic 0.148ns (43.113%) route 0.195ns (56.887%))
Logic Levels: 0
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.200ns
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.560 0.901 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
SLICE_X24Y5 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]/C
------------------------------------------------------------------- -------------------
SLICE_X24Y5 FDRE (Prop_fdre_C_Q) 0.148 1.049 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]/Q
net (fo=1, routed) 0.195 1.244 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[53]
SLICE_X21Y3 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][120]/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.830 1.200 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
SLICE_X21Y3 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][120]/C
clock pessimism -0.034 1.166
SLICE_X21Y3 FDRE (Hold_fdre_C_D) 0.018 1.184 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][120]
-------------------------------------------------------------------
required time -1.184
arrival time 1.244
-------------------------------------------------------------------
slack 0.060
Slack (MET) : 0.064ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr_reg[13]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][7]_srl6/D
(rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.260ns (logic 0.141ns (54.255%) route 0.119ns (45.745%))
Logic Levels: 0
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.192ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.282ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/m_axi_s2mm_aclk
SLICE_X25Y15 FDRE r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr_reg[13]/C
------------------------------------------------------------------- -------------------
SLICE_X25Y15 FDRE (Prop_fdre_C_Q) 0.141 1.038 r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr_reg[13]/Q
net (fo=2, routed) 0.119 1.156 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[15]
SLICE_X24Y15 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][7]_srl6/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.822 1.192 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
SLICE_X24Y15 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][7]_srl6/CLK
clock pessimism -0.282 0.910
SLICE_X24Y15 SRL16E (Hold_srl16e_CLK_D)
0.183 1.093 u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][7]_srl6
-------------------------------------------------------------------
required time -1.093
arrival time 1.156
-------------------------------------------------------------------
slack 0.064
Slack (MET) : 0.067ns (arrival time - required time)
Source: u_pl_top/u_rhs2116_top/u_transmit_config/sw_data_0_reg[44]/C
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_channel_switch/new_data_reg[44]/D
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.422ns (logic 0.227ns (53.731%) route 0.195ns (46.269%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.263ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.198ns
Source Clock Delay (SCD): 0.901ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.560 0.901 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X21Y44 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/sw_data_0_reg[44]/C
------------------------------------------------------------------- -------------------
SLICE_X21Y44 FDCE (Prop_fdce_C_Q) 0.128 1.029 r u_pl_top/u_rhs2116_top/u_transmit_config/sw_data_0_reg[44]/Q
net (fo=1, routed) 0.195 1.224 u_pl_top/u_rhs2116_top/u_transmit_config/sw_data_0[44]
SLICE_X22Y43 LUT3 (Prop_lut3_I1_O) 0.099 1.323 r u_pl_top/u_rhs2116_top/u_transmit_config/new_data[44]_i_1/O
net (fo=1, routed) 0.000 1.323 u_pl_top/u_channel_switch/D[44]
SLICE_X22Y43 FDCE r u_pl_top/u_channel_switch/new_data_reg[44]/D
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.828 1.198 u_pl_top/u_channel_switch/clk
SLICE_X22Y43 FDCE r u_pl_top/u_channel_switch/new_data_reg[44]/C
clock pessimism -0.034 1.164
SLICE_X22Y43 FDCE (Hold_fdce_C_D) 0.092 1.256 u_pl_top/u_channel_switch/new_data_reg[44]
-------------------------------------------------------------------
required time -1.256
arrival time 1.323
-------------------------------------------------------------------
slack 0.067
Slack (MET) : 0.070ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/DP/WADR1
(rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: clk_fpga_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 0.395ns (logic 0.141ns (35.698%) route 0.254ns (64.302%))
Logic Levels: 0
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.199ns
Source Clock Delay (SCD): 0.902ns
Clock Pessimism Removal (CPR): 0.281ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.561 0.902 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
SLICE_X23Y0 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X23Y0 FDRE (Prop_fdre_C_Q) 0.141 1.043 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
net (fo=6, routed) 0.254 1.296 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/A1
SLICE_X24Y0 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/DP/WADR1
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.829 1.199 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/WCLK
SLICE_X24Y0 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/DP/CLK
clock pessimism -0.281 0.918
SLICE_X24Y0 RAMD32 (Hold_ramd32_CLK_WADR1)
0.309 1.227 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0/DP
-------------------------------------------------------------------
required time -1.227
arrival time 1.296
-------------------------------------------------------------------
slack 0.070
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fpga_0
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X2Y8 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X2Y8 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X1Y8 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X1Y8 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X1Y7 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X1Y7 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X1Y9 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X1Y9 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB18_X1Y26 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X1Y6 u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/CLKARDCLK
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA/CLK
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA/CLK
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA_D1/CLK
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA_D1/CLK
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB/CLK
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB/CLK
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB_D1/CLK
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB_D1/CLK
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMC/CLK
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMC/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA_D1/CLK
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMA_D1/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB/CLK
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB_D1/CLK
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMB_D1/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMC/CLK
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X34Y16 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_15_0_5/RAMC/CLK
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: clk_fpga_0
To Clock: clk_fpga_0
Setup : 0 Failing Endpoints, Worst Slack 1.084ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 1.187ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][1]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.338ns (logic 0.538ns (6.452%) route 7.800ns (93.548%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.093ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.301ns = ( 12.301 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.359 10.832 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X39Y98 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][1]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.308 12.301 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X39Y98 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][1]/C
clock pessimism 0.101 12.401
clock uncertainty -0.154 12.247
SLICE_X39Y98 FDCE (Recov_fdce_C_CLR) -0.331 11.916 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][1]
-------------------------------------------------------------------
required time 11.916
arrival time -10.832
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][25]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.338ns (logic 0.538ns (6.452%) route 7.800ns (93.548%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.093ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.301ns = ( 12.301 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.359 10.832 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X39Y98 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][25]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.308 12.301 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X39Y98 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][25]/C
clock pessimism 0.101 12.401
clock uncertainty -0.154 12.247
SLICE_X39Y98 FDCE (Recov_fdce_C_CLR) -0.331 11.916 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][25]
-------------------------------------------------------------------
required time 11.916
arrival time -10.832
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][3]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.338ns (logic 0.538ns (6.452%) route 7.800ns (93.548%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.093ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.301ns = ( 12.301 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.359 10.832 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X39Y98 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][3]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.308 12.301 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X39Y98 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][3]/C
clock pessimism 0.101 12.401
clock uncertainty -0.154 12.247
SLICE_X39Y98 FDCE (Recov_fdce_C_CLR) -0.331 11.916 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][3]
-------------------------------------------------------------------
required time 11.916
arrival time -10.832
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][4]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.338ns (logic 0.538ns (6.452%) route 7.800ns (93.548%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.093ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.301ns = ( 12.301 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.359 10.832 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X39Y98 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][4]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.308 12.301 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X39Y98 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][4]/C
clock pessimism 0.101 12.401
clock uncertainty -0.154 12.247
SLICE_X39Y98 FDCE (Recov_fdce_C_CLR) -0.331 11.916 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[43][4]
-------------------------------------------------------------------
required time 11.916
arrival time -10.832
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][23]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.310ns (logic 0.538ns (6.474%) route 7.772ns (93.526%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.160ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.234ns = ( 12.234 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.330 10.804 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X20Y95 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][23]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.241 12.234 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X20Y95 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][23]/C
clock pessimism 0.101 12.334
clock uncertainty -0.154 12.180
SLICE_X20Y95 FDCE (Recov_fdce_C_CLR) -0.292 11.888 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][23]
-------------------------------------------------------------------
required time 11.888
arrival time -10.804
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][28]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.310ns (logic 0.538ns (6.474%) route 7.772ns (93.526%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.160ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.234ns = ( 12.234 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.330 10.804 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X20Y95 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][28]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.241 12.234 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X20Y95 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][28]/C
clock pessimism 0.101 12.334
clock uncertainty -0.154 12.180
SLICE_X20Y95 FDCE (Recov_fdce_C_CLR) -0.292 11.888 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][28]
-------------------------------------------------------------------
required time 11.888
arrival time -10.804
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][2]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.310ns (logic 0.538ns (6.474%) route 7.772ns (93.526%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.160ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.234ns = ( 12.234 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.330 10.804 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X20Y95 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][2]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.241 12.234 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X20Y95 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][2]/C
clock pessimism 0.101 12.334
clock uncertainty -0.154 12.180
SLICE_X20Y95 FDCE (Recov_fdce_C_CLR) -0.292 11.888 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][2]
-------------------------------------------------------------------
required time 11.888
arrival time -10.804
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.084ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][9]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.310ns (logic 0.538ns (6.474%) route 7.772ns (93.526%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.160ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.234ns = ( 12.234 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.330 10.804 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X20Y95 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][9]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.241 12.234 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X20Y95 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][9]/C
clock pessimism 0.101 12.334
clock uncertainty -0.154 12.180
SLICE_X20Y95 FDCE (Recov_fdce_C_CLR) -0.292 11.888 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[42][9]
-------------------------------------------------------------------
required time 11.888
arrival time -10.804
-------------------------------------------------------------------
slack 1.084
Slack (MET) : 1.104ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[0][9]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.289ns (logic 0.538ns (6.490%) route 7.751ns (93.510%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.160ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.234ns = ( 12.234 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.310 10.783 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X20Y96 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[0][9]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.241 12.234 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X20Y96 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[0][9]/C
clock pessimism 0.101 12.334
clock uncertainty -0.154 12.180
SLICE_X20Y96 FDCE (Recov_fdce_C_CLR) -0.292 11.888 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[0][9]
-------------------------------------------------------------------
required time 11.888
arrival time -10.783
-------------------------------------------------------------------
slack 1.104
Slack (MET) : 1.114ns (required time - arrival time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[46][12]/CLR
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 8.244ns (logic 0.538ns (6.526%) route 7.706ns (93.474%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.157ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.237ns = ( 12.237 - 10.000 )
Source Clock Delay (SCD): 2.494ns
Clock Pessimism Removal (CPR): 0.101ns
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.008 1.008 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 1.093 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.401 2.494 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.433 2.927 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 1.442 4.369 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.105 4.474 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 6.264 10.738 u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tdata_reg[7]_0
SLICE_X35Y99 FDCE f u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[46][12]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
10.000 10.000 r
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.915 10.915 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 10.992 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 1.244 12.237 u_pl_top/u_upload_top/u_upload_sort/clk
SLICE_X35Y99 FDCE r u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[46][12]/C
clock pessimism 0.101 12.337
clock uncertainty -0.154 12.183
SLICE_X35Y99 FDCE (Recov_fdce_C_CLR) -0.331 11.852 u_pl_top/u_upload_top/u_upload_sort/record_rx_reg[46][12]
-------------------------------------------------------------------
required time 11.852
arrival time -10.738
-------------------------------------------------------------------
slack 1.114
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.187ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[4][1]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.379ns (logic 0.209ns (15.152%) route 1.170ns (84.848%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.259ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.190ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.452 2.276 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X20Y30 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[4][1]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.820 1.190 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X20Y30 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[4][1]/C
clock pessimism -0.034 1.156
SLICE_X20Y30 FDCE (Remov_fdce_C_CLR) -0.067 1.089 u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[4][1]
-------------------------------------------------------------------
required time -1.089
arrival time 2.276
-------------------------------------------------------------------
slack 1.187
Slack (MET) : 1.187ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[5][1]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.379ns (logic 0.209ns (15.152%) route 1.170ns (84.848%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.259ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.190ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.452 2.276 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X20Y30 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[5][1]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.820 1.190 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X20Y30 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[5][1]/C
clock pessimism -0.034 1.156
SLICE_X20Y30 FDCE (Remov_fdce_C_CLR) -0.067 1.089 u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[5][1]
-------------------------------------------------------------------
required time -1.089
arrival time 2.276
-------------------------------------------------------------------
slack 1.187
Slack (MET) : 1.187ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[6][1]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.379ns (logic 0.209ns (15.152%) route 1.170ns (84.848%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.259ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.190ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.452 2.276 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X20Y30 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[6][1]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.820 1.190 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X20Y30 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[6][1]/C
clock pessimism -0.034 1.156
SLICE_X20Y30 FDCE (Remov_fdce_C_CLR) -0.067 1.089 u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[6][1]
-------------------------------------------------------------------
required time -1.089
arrival time 2.276
-------------------------------------------------------------------
slack 1.187
Slack (MET) : 1.187ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[7][1]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.379ns (logic 0.209ns (15.152%) route 1.170ns (84.848%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.259ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.190ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.034ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.452 2.276 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X20Y30 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[7][1]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.820 1.190 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X20Y30 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[7][1]/C
clock pessimism -0.034 1.156
SLICE_X20Y30 FDCE (Remov_fdce_C_CLR) -0.067 1.089 u_pl_top/u_rhs2116_top/u_transmit_config/stim_trim_n_reg[7][1]
-------------------------------------------------------------------
required time -1.089
arrival time 2.276
-------------------------------------------------------------------
slack 1.187
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][14]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][14]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][14]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][14]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][15]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][15]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][15]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][15]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][19]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][19]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][19]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][19]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][20]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][20]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][20]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][20]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][22]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][22]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][22]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][22]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
Slack (MET) : 1.231ns (arrival time - required time)
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][23]/CLR
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 1.167ns (logic 0.209ns (17.915%) route 0.958ns (82.084%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.187ns
Source Clock Delay (SCD): 0.897ns
Clock Pessimism Removal (CPR): 0.262ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.315 0.315 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.556 0.897 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X24Y34 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
------------------------------------------------------------------- -------------------
SLICE_X24Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
net (fo=249, routed) 0.719 1.779 u_ps_a9_1/rst_n[0]
SLICE_X16Y16 LUT1 (Prop_lut1_I0_O) 0.045 1.824 f u_ps_a9_1/FSM_sequential_state[1]_i_2/O
net (fo=11207, routed) 0.239 2.063 u_pl_top/u_rhs2116_top/u_transmit_config/bram_dout_reg[31]_1
SLICE_X23Y20 FDCE f u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][23]/CLR
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 0.341 0.341 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=19790, routed) 0.817 1.187 u_pl_top/u_rhs2116_top/u_transmit_config/clk
SLICE_X23Y20 FDCE r u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][23]/C
clock pessimism -0.262 0.925
SLICE_X23Y20 FDCE (Remov_fdce_C_CLR) -0.092 0.833 u_pl_top/u_rhs2116_top/u_transmit_config/dds_phase_off_reg[12][23]
-------------------------------------------------------------------
required time -0.833
arrival time 2.063
-------------------------------------------------------------------
slack 1.231
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