183 lines
11 KiB
Plaintext
183 lines
11 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Sun Aug 4 13:44:39 2024
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| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
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| Command : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
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| Design : c64pro_top
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| Device : xc7z010clg400-2
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 1.263 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 1.145 |
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| Device Static (W) | 0.118 |
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| Effective TJA (C/W) | 11.5 |
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| Max Ambient (C) | 70.4 |
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| Junction Temperature (C) | 39.6 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+--------------------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+--------------------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.033 | 3 | --- | --- |
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| Slice Logic | 0.021 | 37606 | --- | --- |
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| LUT as Logic | 0.019 | 11627 | 17600 | 66.06 |
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| CARRY4 | <0.001 | 565 | 4400 | 12.84 |
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| Register | <0.001 | 18749 | 35200 | 53.26 |
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| LUT as Distributed RAM | <0.001 | 444 | 6000 | 7.40 |
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| F7/F8 Muxes | <0.001 | 1473 | 17600 | 8.37 |
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| LUT as Shift Register | <0.001 | 141 | 6000 | 2.35 |
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| BUFG | <0.001 | 4 | 32 | 12.50 |
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| Others | 0.000 | 1299 | --- | --- |
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| Signals | 0.033 | 26449 | --- | --- |
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| Block RAM | 0.012 | 26 | 60 | 43.33 |
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| I/O | 0.003 | 76 | 100 | 76.00 |
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| PS7 | 1.043 | 1 | --- | --- |
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| Static Power | 0.118 | | | |
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| Total | 1.263 | | | |
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+--------------------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Vccint | 1.000 | 0.105 | 0.098 | 0.007 | NA | Unspecified | NA |
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| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | NA | Unspecified | NA |
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| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccbram | 1.000 | 0.003 | 0.001 | 0.002 | NA | Unspecified | NA |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccpint | 1.000 | 0.573 | 0.547 | 0.025 | NA | Unspecified | NA |
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| Vccpaux | 1.800 | 0.035 | 0.025 | 0.010 | NA | Unspecified | NA |
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| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA |
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| Vcco_ddr | 1.350 | 0.311 | 0.309 | 0.002 | NA | Unspecified | NA |
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| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
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| Vcco_mio1 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 11.5 |
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| Airflow (LFM) | 250 |
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| Heat Sink | none |
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| ThetaSA (C/W) | 0.0 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 8to11 (8 to 11 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+------------------------+
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2.2 Clock Constraints
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---------------------
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+------------+--------------------------------------------------------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+------------+--------------------------------------------------------------------------+-----------------+
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| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
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+------------+--------------------------------------------------------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+-------------------------------+-----------+
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| Name | Power (W) |
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+-------------------------------+-----------+
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| c64pro_top | 1.145 |
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| u_pl_top | 0.043 |
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| u_eeg_top | 0.007 |
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| u_eeg_upload | 0.002 |
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| u_rhs2116_top | 0.017 |
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| u_sine_wave_gen | 0.003 |
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| u_trans_distribute | 0.003 |
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| u_transmit_config | 0.005 |
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| u_upload_top | 0.018 |
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| u_upload_config | 0.005 |
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| u_upload_protocol_intan | 0.002 |
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| u_upload_protocol_ql | 0.003 |
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| u_upload_sort | 0.008 |
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| u_ps_a9_1 | 1.098 |
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| design_a9_1_i | 1.089 |
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| axi_dma_0 | 0.002 |
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| axi_dma_1 | 0.003 |
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| axi_iic_0 | 0.001 |
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| axi_iic_1 | 0.001 |
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| axi_smc | 0.010 |
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| axis_data_fifo_0 | 0.004 |
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| axis_data_fifo_1 | 0.006 |
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| processing_system7_0 | 1.043 |
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| smartconnect_0 | 0.016 |
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+-------------------------------+-----------+
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