98 lines
2.4 KiB
Verilog
98 lines
2.4 KiB
Verilog
`timescale 1 ns / 1 ps
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module stim_event_collect#
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(
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parameter CHIPSET_QTY = 4
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)
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(
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input clk ,
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input rst_n ,
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input [32*CHIPSET_QTY-1:0] event_in_arrary ,
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output [32-1:0] event_out
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam HOLD_CLKS = CHIPSET_QTY ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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wire [32-1:0] event_in[0:CHIPSET_QTY-1];
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reg [32-1:0] event_in_r[0:CHIPSET_QTY-1];
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reg update[0:CHIPSET_QTY-1];
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reg [ 4-1:0] cnt[0:CHIPSET_QTY-1];
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reg [32-1:0] event_r;
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reg [ 4-1:0] n;
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genvar i;
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//*****************************************************************************
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : rrr
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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event_in_r[i] <= 0;
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else
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event_in_r[i] <= event_in[i];
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end
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : update_hold
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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cnt[i] <= 0;
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else if (event_in_r[i] != event_in[i])
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cnt[i] <= 0;
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else if (cnt[i] != HOLD_CLKS - 1)
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cnt[i] <= cnt[i] + 1'b1;
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end
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : update_check
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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update[i] <= 1'b0;
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else if (event_in_r[i] != event_in[i])
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update[i] <= 1'b1;
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else if (cnt[i] == HOLD_CLKS - 1)
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update[i] <= 1'b0;
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end
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end
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endgenerate
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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n <= 0;
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else if (n < CHIPSET_QTY-1)
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n <= n + 1'b1;
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else
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n <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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event_r <= 0;
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else if (update[n])
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event_r <= event_in[n];
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
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assign event_in[i] = event_in_arrary[32*i+31 : 32*i];
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end
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endgenerate
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assign event_out = event_r;
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endmodule
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