152 lines
4.1 KiB
Verilog
152 lines
4.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module eeg_config#
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(
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parameter SPIS_QTY = 4 ,
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parameter SPI_DATA_WIDTH = 8
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output reg [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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//------------------------------------------ eeg
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output [32-1:0] eeg_er ,
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output [32-1:0] eeg_cr ,
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input [32-1:0] eeg_sr ,
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output [32*SPIS_QTY-1:0] eeg_tr_array ,
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input [32*SPIS_QTY-1:0] eeg_rr_array ,
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output reg eeg_sr_r_evt
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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localparam BRAM_ADDR_EEG_ER = 13'h0040;
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localparam BRAM_ADDR_EEG_CR = 13'h0044;
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localparam BRAM_ADDR_EEG_SR = 13'h0048;
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localparam BRAM_ADDR_EEG_TR = 13'h0100;
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localparam BRAM_ADDR_EEG_RR = 13'h0200;
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localparam BRAM_ADDR_EEG_TR_MASK = 13'h1F00;
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localparam BRAM_ADDR_EEG_RR_MASK = 13'h1F00;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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wire bram_wr_valid ;
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wire bram_rd_valid ;
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reg [32-1:0] eeg_er_r ;
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reg [32-1:0] eeg_cr_r ;
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reg [32-1:0] eeg_tr_r[SPIS_QTY-1:0] ;
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wire [32-1:0] eeg_rr_r[SPIS_QTY-1:0] ;
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integer n;
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genvar i;
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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test_data <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
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test_data <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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eeg_er_r <= 0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EEG_ER ) ) begin
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eeg_er_r <= bram_din;
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end else begin
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eeg_er_r <= 0;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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eeg_cr_r <= 0;
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end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EEG_CR ) ) begin
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eeg_cr_r <= bram_din;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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n = 0;
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while(n<SPIS_QTY) begin
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eeg_tr_r[n] <= 0;
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_EEG_TR_MASK) == BRAM_ADDR_EEG_TR ) )
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eeg_tr_r[bram_addr[7:2]] <= bram_din;
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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bram_dout <= 0;
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end else if ( bram_rd_valid ) begin
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if ( bram_addr == BRAM_ADDR_TEST_RO )
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bram_dout <= 32'h12345678;
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if ( bram_addr == BRAM_ADDR_TEST_RW )
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bram_dout <= test_data;
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if ( bram_addr == BRAM_ADDR_EEG_SR ) begin
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bram_dout <= eeg_sr;
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eeg_sr_r_evt <= 1'b1;
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end
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if ( (bram_addr & BRAM_ADDR_EEG_RR_MASK) == BRAM_ADDR_EEG_RR )
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bram_dout <= eeg_rr_r[bram_addr[7:2]];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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eeg_sr_r_evt <= 1'b0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_EEG_SR ) )
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eeg_sr_r_evt <= 1'b1;
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else
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eeg_sr_r_evt <= 1'b0;
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign bram_wr_valid = bram_en && (bram_we == 4'hF);
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assign bram_rd_valid = bram_en && (bram_we == 4'h0);
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generate
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for(i=0;i<SPIS_QTY;i=i+1) begin : mapping
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assign eeg_tr_array[32*i+31 : 32*i] = eeg_tr_r[i];
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assign eeg_rr_r[i] = eeg_rr_array[32*i+31 : 32*i];
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end
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endgenerate
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assign eeg_er = eeg_er_r;
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assign eeg_cr = eeg_cr_r;
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endmodule
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