1110 lines
659 KiB
Plaintext
1110 lines
659 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Sun Aug 4 13:42:57 2024
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| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
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| Command : report_control_sets -verbose -file c64pro_top_control_sets_placed.rpt
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| Design : c64pro_top
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| Device : xc7z010
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Control Set Information
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Table of Contents
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-----------------
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1. Summary
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2. Histogram
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3. Flip-Flop Distribution
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4. Detailed Control Set Information
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1. Summary
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----------
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+----------------------------------------------------------+-------+
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| Status | Count |
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+----------------------------------------------------------+-------+
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| Total control sets | 1031 |
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| Minimum number of control sets | 1031 |
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| Addition due to synthesis replication | 0 |
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| Addition due to physical synthesis replication | 0 |
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| Unused register locations in slices containing registers | 2651 |
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+----------------------------------------------------------+-------+
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* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
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** Run report_qor_suggestions for automated merging and remapping suggestions
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2. Histogram
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------------
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+--------------------+-------+
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| Fanout | Count |
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+--------------------+-------+
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| Total control sets | 1031 |
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| >= 0 to < 4 | 214 |
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| >= 4 to < 6 | 69 |
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| >= 6 to < 8 | 47 |
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| >= 8 to < 10 | 176 |
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| >= 10 to < 12 | 46 |
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| >= 12 to < 14 | 29 |
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| >= 14 to < 16 | 9 |
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| >= 16 | 441 |
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+--------------------+-------+
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* Control sets can be remapped at either synth_design or opt_design
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3. Flip-Flop Distribution
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-------------------------
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| No | No | No | 887 | 151 |
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| No | No | Yes | 1228 | 271 |
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| No | Yes | No | 1377 | 382 |
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| Yes | No | No | 1641 | 344 |
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| Yes | No | Yes | 10115 | 2393 |
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| Yes | Yes | No | 3501 | 774 |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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4. Detailed Control Set Information
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-----------------------------------
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/sig_addr_posted_cntr_reg[3]_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/p_3_in | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_start_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/gen_wsplitter.awtrans_cntr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]_0 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_token_cntr[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/sclk_r_i_1__6_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/sclk_r_i_1__5_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/sclk_r_i_1__4_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/p_3_in | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/sclk_r_i_1__3_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/event_r_reg[9]_0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/sclk_r_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_channel_switch/u_adg1414_if/sclk_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/gen_srls[1].srl_nx1/shift | | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/sclk_r_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/sclk_r_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.gen_rthread_loop[0].r_split_fifo/gen_srls[0].srl_nx1/shift_qual | | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/sclk_r_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/gen_rsplitter.artrans_cntr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/gen_rsplitter.ar_split_state_reg_1 | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.gen_wthread_loop[0].b_split_fifo/gen_srls[0].srl_nx1/shift_qual | | 1 | 1 | 1.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/cs_r[1] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/mi_handler_m_sc_areset | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/s_sc_areset_pipe | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/cs_r[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 1 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 2 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/sig_sm_ld_dre_cmd | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 2 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_m_valid_out_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr[9]_i_1_n_0 | 1 | 2 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_srls[2].srl_nx1/shift_qual | | 2 | 2 | 1.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_CTRL_I/CI | | 1 | 2 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_CTRL_I/CI | | 1 | 2 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_exit_pipeline/m09_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m09_nodes/m09_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_exit_pipeline/m04_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/update_hold[3].cnt[3][2]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_nodes/m02_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_nodes/m01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m02_exit_pipeline/m02_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m01_exit_pipeline/m01_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_exit_pipeline/m03_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m03_nodes/m03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m04_nodes/m04_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_exit_pipeline/m05_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_exit_pipeline/m06_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_nodes/m07_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_b_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_exit_pipeline/m08_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m05_nodes/m05_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_r_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m06_nodes/m06_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m08_nodes/m08_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/m07_exit_pipeline/m07_exit/inst/xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/reset_pol | 1 | 3 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/Tx_data_exists_sgl | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[8] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 4 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/mutant_x_chan | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/sclr_i | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/READ_FIFO_I/Rc_Data_Exists | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/BITCNT/q_int[0]_i_1__1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 4 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/m_axi_trans_tvalid_reg_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_CTRL_I/Data_Exists_DFF_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/m_axi_trans_tvalid_reg_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 4 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_1[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/Tx_data_exists_sgl | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[8] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/READ_FIFO_I/Rc_Data_Exists | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/s_axi_rx_tdata_r1 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/BITCNT/q_int[0]_i_1__1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/m_axi_trans_tvalid_reg_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/s_axi_lite_awaddr[6] | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_srls[16].srl_nx1/shift_qual | | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/areset_r_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.gen_rthread_loop[0].r_split_fifo/fifoaddr[3]_i_1__1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/fifoaddr[3]_i_1__3_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/EXT_LPF/lpf_int | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/fifoaddr[3]_i_1__2_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/m_axi_trans_tvalid_reg_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/fifoaddr[3]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_pinc_poff_in.i_config_multichan.i_config_tready_reg/E[0] | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/sclr_i | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_pipelined.mesg_reg | | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_CTRL_I/Data_Exists_DFF_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.gen_wthread_loop[0].b_split_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_coelsc_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_coelsc_cmd_cmplt_reg_i_1_n_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/areset_r_0 | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_en[3]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 4 | 1.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/eeg_cr_r_reg[31][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/fifoaddr[3]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/areset | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/update_hold[2].cnt[2][3]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/update_hold[1].cnt[1][3]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/update_hold[0].cnt[0][3]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 4 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/spi_cmd_chip[4]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/gen_pipelined.mesg_reg | | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/gen_srls[4].srl_nx1/shift_qual | | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[7].srl_nx1/shift | | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/gen_endpoint.w_push_done_reg[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset_d | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset_d | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/wroute_vacancy | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_wroute_reg.wroute_i[10]_i_1_n_0 | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/wroute_vacancy | | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[1136]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[10]_i_1_n_0 | 1 | 5 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[11] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 5 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[11] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 5 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[1144]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[146]_i_1__0_n_0 | 1 | 6 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_detection_int/p_0_in | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 6 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 6 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 6 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/AXI_Bus2IP_Reset | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/m_axi_trans_tvalid_reg_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/m_axi_trans_tvalid_reg_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/AXI_Bus2IP_Reset | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[1144]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[146]_i_1_n_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_event_collect/event_r[9]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 6 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4LITE.I_AXI_LITE/s_axi_aresetn_0 | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/areset_r_0 | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/m_axi_trans_tvalid_reg_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/m_axi_trans_tvalid_reg_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 6 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 6 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | 3.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/trigger_collect_tdata | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 6 | 2.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 7 | 1.75 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 7 | 3.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 7 | 1.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 7 | 2.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1][0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 2 | 7 | 3.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[9] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 7 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 7 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[9] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 7 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/s2mm_all_idle | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 7 | 3.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/mm2s_all_idle | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/r_beats[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/read_flag | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/ch[7]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/r_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[0][7]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/t_cnt[7]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[2][7]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/recv_data[1][7]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/t_tvalid_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/r_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/recv_data[0][7]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/recv_data | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/recv_data[2][7]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/t_cnt[7]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/recv_data[1][7]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/t_tvalid_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/t_cnt[7]_i_1__3_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/recv_data | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/r_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/recv_data[0][7]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/recv_data[1][7]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/recv_data[2][7]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/t_tvalid_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_channel_switch/u_adg1414_if/trans_cnt[7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_15[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/I2CDATA_REG/data_int[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/DYN_MASTER_I/rdByteCntr[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/ce | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/READ_FIFO_I/CI | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/i2c_header_en | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/data_i2c_i0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/ce | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/CI | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/ce | | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/i2c_header_en | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/data_i2c_i0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/ce | | 2 | 8 | 4.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/I2CDATA_REG/data_int[7]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/r_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[0][7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[2][7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/recv_data[1][7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_cnt[7]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/t_tvalid_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/DYN_MASTER_I/rdByteCntr[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/Tx_fifo_rst | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_8[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_10[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_9[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/cnv_drdy_r_reg[2]_11[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/READ_FIFO_I/CI | | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_19[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_18[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_11[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/CI | | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_17[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_22[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_19[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_24[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_6[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_18[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg[0] | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_13[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/SS[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/ch[7]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/scan_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_25[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_9[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_14[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_23[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_13[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/s_axi_lite_wdata[16][0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_16[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/read_flag | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_m_valid_out_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_clr_dbc_reg_reg[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_21[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_12[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_10[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_20[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_15[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_8[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[4][7]_i_4_7[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg[0] | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_12[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/areset_r_0 | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tvalid | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/m_axis_record_tdata[7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/m_axis_record_tvalid_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/read_flag | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | 8.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 8 | 2.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/r_tlast_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/recv_cnt[7]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/ch[7]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/trans_cnt | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/u_ads1299_spi/t_tready_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/u_ads1299_spi/read_flag | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_20[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 8 | 1.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/ch[7]_i_1__3_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[100][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_7[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/clk_cnt_reg[5][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_14[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[6][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_16[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_6[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_17[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 8 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_10[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_8[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 8 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_11[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_9[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 1 | 8 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[12][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[5][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[7][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[1][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[13][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[8][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[14][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[3][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[2][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[6][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[11][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[10][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/ar_cnt[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.w_split_fifo/E[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/b_cnt[8]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/b_cnt[8]_i_1_n_0 | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/w_cnt[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 9 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[15][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 2 | 9 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[9][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 9 | 1.80 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/sine_data[4][8]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 9 | 4.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_si_handler/gen_si_handler.gen_request_counters.gen_req_counter[3].inst_req_counter/E[0] | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_si_handler/areset_r | 2 | 10 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[2].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[3].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 4 | 10 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[1].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 10 | 3.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 10 | 5.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/SR[0] | 4 | 10 | 2.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 10 | 3.33 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/SR[0] | 3 | 10 | 3.33 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[2] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[0] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[6] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[7] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[4] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[3] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[1] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[5] | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 4 | 10 | 2.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/SETUP_CNT/q_int[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/IIC_CONTROL_I/FSM_onehot_scl_state[9]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[3] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[4] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[5] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[7] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[1] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[0] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[2] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus2IIC_WrCE[6] | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/SETUP_CNT/q_int[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/FSM_onehot_scl_state[9]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__0_n_0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 3 | 10 | 3.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/allow_transfer | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/inst_si_handler/gen_si_handler.gen_request_counters.gen_req_counter[7].inst_req_counter/areset_r_reg[0] | 2 | 10 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/inst_si_handler/gen_si_handler.gen_request_counters.gen_req_counter[3].inst_req_counter/E[0] | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/inst_si_handler/areset_r | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_mi_handler/gen_normal_area.gen_fi_regulator.inst_fi_regulator/allow_transfer | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_si_handler/gen_si_handler.gen_request_counters.gen_req_counter[7].inst_req_counter/areset_r_reg[0] | 2 | 10 | 5.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 11 | 2.75 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 11 | 2.75 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 11 | 2.75 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 3 | 11 | 3.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/ar_addr_d[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/aw_addr[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/s_sc_handshake[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i[11]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.s_axi_rid_i | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 4 | 12 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[19]_i_1_n_0 | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 12 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/s_sc_handshake[0] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 3 | 12 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_pipelined.mesg_reg_reg[1] | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 4 | 12 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst | 4 | 12 | 3.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 12 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_monitor/pulse_ms_reg_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 12 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/gen_id_reg.s_rid_i0 | | 2 | 12 | 6.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_transaction_regulator/inst/gen_endpoint.gen_r_singleorder.r_singleorder/gen_id_reg.s_rid_i0 | | 3 | 12 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 3 | 12 | 4.00 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 2 | 13 | 6.50 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 2 | 13 | 6.50 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 3 | 13 | 4.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 13 | 3.25 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/m_axi_mm2s_rlast_0 | 3 | 14 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/spi_done | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 14 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/spi_done | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 14 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/spi_done | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 14 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 14 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/spi_done | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 14 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg_ns | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 2 | 15 | 7.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_led_wifi/u_breath_gen/breath_data_0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 15 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/crc16[15]_i_1__0_n_4 | u_pl_top/u_upload_top/u_upload_protocol_intan/upload_round_qty_1 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/done_r_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/stim_state0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/crc16[15]_i_1_n_4 | u_pl_top/u_upload_top/u_upload_protocol_ql/upload_round_qty | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[0].u_ads1299_arrange/time_cnt[15]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[2].u_ads1299_arrange/time_cnt[15]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[3].u_ads1299_arrange/time_cnt[15]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_im0_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/done_r_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/stim_state0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/transmit_arrange[1].u_ads1299_arrange/time_cnt[15]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/is_end_reg | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/stim_state0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/done_r_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/stim_state0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 16 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 16 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/polarity_mark[15]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_led_wifi/u_breath_gen/ms_cnt[0]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 16 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/polarity_mark[15]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/done_r_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 16 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/polarity_mark[15]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/polarity_mark[15]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 16 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/eeg_er_r[3]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 17 | 3.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_wsplitter.s_axi_awid_d | | 3 | 17 | 5.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/gen_rsplitter.s_axi_arid_d | | 3 | 18 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/areset | 4 | 18 | 4.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 3 | 19 | 6.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 20 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[1] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 3 | 20 | 6.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/m_aruser | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 4 | 20 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/ch | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 20 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 20 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 5 | 20 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[22]_0[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 3 | 20 | 6.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[19]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 5 | 20 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 3 | 21 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 21 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 21 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 21 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/p_13_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 21 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 21 | 4.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 21 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 21 | 4.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/p_12_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 22 | 3.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/p_10_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 22 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 5 | 22 | 4.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/p_11_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 22 | 3.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 23 | 5.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[142]_i_1_n_0 | | 6 | 23 | 3.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 3 | 23 | 7.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_cnv_res_collect/FSM_sequential_cstate_reg_0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 23 | 3.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[142]_i_1_n_0 | | 5 | 23 | 4.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 6 | 23 | 3.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[45][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[89][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[61][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[73][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[5][7]_i_3_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[57][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[53][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[85][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[61][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[41][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[77][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[53][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[9][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[5][7]_i_3_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[9][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/areset_r | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[109][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[69][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[97][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[93][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[65][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[57][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[5][7]_i_3_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[33][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[81][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[45][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[33][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[29][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[121][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[101][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[3][7]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 24 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[17][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[37][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[25][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[105][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[125][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[21][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_config/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/areset_r | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[37][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 24 | 3.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[21][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_config/eeg_cr_r_reg[31]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[17][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[113][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_config/eeg_cr_r_reg[31]_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_config/eeg_cr_r_reg[31]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[41][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[13][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[49][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[3][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[3][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[13][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[29][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 3 | 24 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/areset_r | 4 | 24 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[25][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 24 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[117][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 24 | 2.18 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/areset_r | 5 | 24 | 4.80 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/pre_message[49][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_si_handler/s_sc_valid | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/areset_r | 7 | 24 | 3.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_xfer_reg_ns | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/areset | 5 | 25 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/SR[0] | 4 | 25 | 6.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/SR[0] | 6 | 25 | 4.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 26 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | u_ps_a9_1/design_a9_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 26 | 3.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/sig_coelsc_tag_reg0 | 4 | 27 | 6.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 4 | 27 | 6.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/ram_rd_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rst_d1_inst/ram_wr_en_pf | u_ps_a9_1/design_a9_1_i/axis_data_fifo_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_si_handler/areset_r | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_b_node/inst/inst_si_handler/areset_r | 8 | 30 | 3.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_51[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_30[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_55[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_40[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_25[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_23[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_36[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_42[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 12 | 32 | 2.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_9[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_34[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_50[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_49[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_54[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_24[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_43[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_44[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_47[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_37[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_21[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_22[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_39[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_52[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_56[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_58[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_59[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_45[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_48[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_53[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_27[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_60[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_6[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_61[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[4][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/package_id[0]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/trigger_word | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/upload_bytes_cnt[31]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/upload_round_qty_1 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/upload_record_bytes_cnt[31]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_intan/upload_rounds_cnt[31]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[4][7]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/package_id[0]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/trigger_word[31]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/upload_bytes_cnt[31]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/upload_round_qty | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/upload_record_bytes_cnt[31]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_protocol_ql/upload_rounds_cnt[31]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[0][7]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/record_tx0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[4][7]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[0][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[0][7]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[0][7]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_8[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_en_a[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_6[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[0][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[0][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/FSM_onehot_cstate_reg[1]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out0 | 9 | 32 | 3.56 |
|
|
| n_2_6399_BUFG | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| n_1_6243_BUFG | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_24[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[15][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[7][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_21[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[5][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/package_overtime_ms[31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_22[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_9[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_6[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[11][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[3]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_18[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_17[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_15[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_13[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_en_a_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[7]_21[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_7[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_26[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_10[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_23[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_en_a[1] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_en_a_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_20[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_11[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_25[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/m_axi_trans_tdata[31]_i_1__1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_we_a[2]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/nstate0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[3]_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/m_axi_trans_tdata[31]_i_1__0_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/nstate0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bram_dout[31]_i_5__0_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/m_axi_trans_tdata[31]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/nstate0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[13][31]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[0][31]_i_2_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[3]_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[15][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[2]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/nstate0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/m_axi_trans_tdata[31]_i_1__2_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_timer/start_clocks_cnt[0]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_5[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/aclken | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/mute_chan | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_19[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_16[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_14[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_transmit_config/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_transmit_config/spi_cmd_valid_reg[3]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_transmit_config/spi_cmd_valid_reg[2]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_transmit_config/spi_cmd_valid_reg[1]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[5][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_off[0][31]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[13][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[4]_12[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/tx_data0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[1136]_i_1__0_n_0 | | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/bbstub_bram_addr_a[3]_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/u_spi_full_duplex_master/spi_flag_reg[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/spi_res_en_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/spi_res_en_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[4][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[1].u_ads1299_if/cnv_res_tdata0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/tx_data0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/u_spi_full_duplex_master/spi_flag_reg[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[0].u_ads1299_if/cnv_res_tdata0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/gen_axilite_conv.axilite_conv_inst/s_axi_rdata_i[31]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[3].u_ads1299_if/cnv_res_tdata0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/spi_flag_reg[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_n[4][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/trans_if[2].u_ads1299_if/cnv_res_tdata0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[0][7]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/p_0_in | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/tx_data0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/u_spi_full_duplex_master/spi_flag_reg[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/spi_res_en_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[0][7]_i_2_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[4][7]_i_2_2[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/u_spi_full_duplex_master/tx_data0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 4 | 32 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/spi_res_en_reg_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[4][7]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 32 | 6.40 |
|
|
| n_0_6087_BUFG | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/stim_trim_p[4][7]_i_2_3[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/FSM_onehot_cstate_reg[1][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_10[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_11[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_46[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_16[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_13[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_15[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_17[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_14[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_12[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_18[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 7 | 32 | 4.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_19[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_28[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_31[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_33[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 13 | 32 | 2.46 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_7[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_8[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/dds_phase_inc[7][31]_i_2_0[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_41[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_35[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_26[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 14 | 32 | 2.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_20[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_29[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_4[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 11 | 32 | 2.91 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_57[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 32 | 3.20 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_38[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 32 | 5.33 |
|
|
| n_3_6555_BUFG | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 32 | 3.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_config/protocol_sel_reg_32[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 32 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/round_end1 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/p_4_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[1].u_trans_arrange/m_axi_trans_tvalid_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 33 | 6.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/p_3_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/gen_wsplitter.awtrans_cntr | | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[3].u_trans_arrange/m_axi_trans_tvalid_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 5 | 33 | 6.60 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_eeg_top/u_eeg_upload/p_2_out | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/gen_rsplitter.artrans_cntr | | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/m_axi_trans_tvalid_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 8 | 33 | 4.12 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/transmit_arrange[2].u_trans_arrange/m_axi_trans_tvalid_reg_1[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 6 | 33 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_r_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter/s_sc_valid | | 9 | 33 | 3.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1088]_i_2_n_0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1088]_i_1_n_0 | 12 | 34 | 2.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/skid_buffer[1090]_i_1__1_n_0 | | 6 | 35 | 5.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_input_cache_type_reg0 | 7 | 35 | 5.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/m_vector_i | | 10 | 35 | 3.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i | | 6 | 35 | 5.83 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_lsh_im0[15]_i_1_n_0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 9 | 36 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_2[0] | 6 | 36 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 7 | 36 | 5.14 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i | | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 6 | 37 | 6.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i | | 6 | 37 | 6.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i | | 5 | 37 | 7.40 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer[2052]_i_1_n_0 | | 7 | 37 | 5.29 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 6 | 39 | 6.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/gpio_core_1/Read_Reg_Rst | 6 | 40 | 6.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_btt_cntr0 | 7 | 40 | 5.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/s_sc_recv[0] | 5 | 40 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1136]_i_1_n_0 | | 13 | 41 | 3.15 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/REG_INTERFACE_I/cr_i_reg[7]_0 | 9 | 41 | 4.56 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 13 | 41 | 3.15 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 7 | 41 | 5.86 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_1/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 8 | 42 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 7 | 42 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1144]_i_1_n_0 | | 9 | 42 | 4.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/m_sc_areset_r | 8 | 42 | 5.25 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_iic_0/U0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/SR[0] | 6 | 42 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 6 | 42 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 7 | 42 | 6.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/skid_buffer[1144]_i_1__0_n_0 | | 9 | 43 | 4.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/USE_SRL_FIFO.sig_wr_fifo | | 6 | 43 | 7.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/m_vector_i | | 6 | 43 | 7.17 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_reg_stall/m_vector_i | | 8 | 43 | 5.38 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1_n_0 | | 10 | 43 | 4.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__0_n_0 | | 11 | 44 | 4.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_sreg/m_vector_i | | 8 | 44 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 8 | 44 | 5.50 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_ok_to_post_rd_addr_reg | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1_n_0 | 7 | 45 | 6.43 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_reg_fifo.inst_reg_fifo/gen_single_rank.data[62]_i_1_n_0 | | 13 | 46 | 3.54 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 7 | 46 | 6.57 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/m_sc_areset_r | 8 | 46 | 5.75 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 6 | 48 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_trigger_top/u_trigger_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 6 | 48 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 6 | 48 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid_buffer[1144]_i_1__2_n_0 | | 9 | 49 | 5.44 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/m_vector_i | | 7 | 49 | 7.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/skid_buffer[1144]_i_1__1_n_0 | | 11 | 49 | 4.45 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/m_vector_i | | 7 | 49 | 7.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_1 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 7 | 53 | 7.57 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.I_S2MM_CMDSTS/dmacr_i_reg[2] | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0[0] | 10 | 53 | 5.30 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/E[0] | u_ps_a9_1/design_a9_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SR[0] | 10 | 54 | 5.40 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 9 | 54 | 6.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/skid_buffer[1144]_i_1_n_0 | | 7 | 54 | 7.71 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/areset | 12 | 55 | 4.58 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/aclken | u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/sclr_i | 14 | 55 | 3.93 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/skid_buffer[1144]_i_1__0_n_0 | | 9 | 55 | 6.11 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 7 | 56 | 8.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/aw_cmd_reg/m_vector_i | | 15 | 60 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.splitter_inst/ar_cmd_reg/m_vector_i | | 16 | 61 | 3.81 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_dma_1/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/SR[0] | 13 | 63 | 4.85 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_stim_monitor/latch_period_reg[9]_0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 10 | 64 | 6.40 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_channel_switch/u_adg1414_if/cstate0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 64 | 7.11 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_channel_switch/u_adg1414_if/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 14 | 64 | 4.57 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/latch_period_reg[9][0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 64 | 7.11 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_channel_switch/new_data_r0 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_run_time/pulse_ms | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/pulse_ms_reg | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 16 | 64 | 4.00 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/peripheral_aresetn[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 9 | 64 | 7.11 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_upload_top/u_upload_sort/ch_list[63]_i_1_n_4 | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 17 | 64 | 3.76 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 15 | 70 | 4.67 |
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| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 16 | 71 | 4.44 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][139]_i_1_n_0 | 10 | 73 | 7.30 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 17 | 74 | 4.35 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/m_sc_areset_r | 14 | 79 | 5.64 |
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|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/rd_addrb_incr | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 15 | 85 | 5.67 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/s_axis_config_tvalid | | 11 | 88 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_sine_wave_gen/aclken | | 16 | 90 | 5.62 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 100 | 7.69 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 14 | 108 | 7.71 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 14 | 112 | 8.00 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | u_pl_top/u_rhs2116_top/u_trans_timer/E[0] | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 25 | 144 | 5.76 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | | 154 | 890 | 5.78 |
|
|
| u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | u_ps_a9_1/bbstub_peripheral_aresetn[0] | 183 | 964 | 5.27 |
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+--------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
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