285 lines
8.5 KiB
Verilog
285 lines
8.5 KiB
Verilog
`timescale 1 ns / 1 ps
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module upload_top#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CHANNLE_QTY = 64 ,
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parameter PRE_MSG_LEN = 128
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output interrupt ,
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input [32-1:0] s_axis_trigger_tdata ,
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input s_axis_trigger_tvalid ,
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output s_axis_trigger_tready ,
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input [32-1:0] s_axis_eeg16_tdata ,
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input s_axis_eeg16_tlast ,
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output s_axis_eeg16_tready ,
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input s_axis_eeg16_tvalid ,
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input [32-1:0] s_axis_eeg24_tdata ,
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input s_axis_eeg24_tlast ,
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output s_axis_eeg24_tready ,
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input s_axis_eeg24_tvalid ,
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input [32-1:0] s_axis_emg_tdata ,
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input s_axis_emg_tlast ,
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output s_axis_emg_tready ,
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input s_axis_emg_tvalid ,
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input [48-1:0] accel_data ,
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input m_axis_record_tfull ,
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output [ 8-1:0] m_axis_record_tdata ,
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output [ 1-1:0] m_axis_record_tkeep ,
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output m_axis_record_tlast ,
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input m_axis_record_tready ,
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output m_axis_record_tvalid ,
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output [ 4-1:0] debug_sig
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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wire pulse_ms ;
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wire [64-1:0] run_time_ms ;
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wire eeg_sel ;
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wire protocol_sel ;
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wire reset_package_id ;
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wire [32-1:0] overtime_ms ;
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wire [ 8*PRE_MSG_LEN-1:0] pre_message_array ;
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wire [ 8-1:0] pre_message_length ;
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wire [ 8*CHANNLE_QTY-1:0] ch_mapping2pc_array ;
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wire [ CHANNLE_QTY-1:0] upload_ch_array ;
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wire [32-1:0] upload_round_qty_set ;
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wire [32-1:0] s_axis_trig_ql_tdata ;
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wire s_axis_trig_ql_tvalid ;
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wire s_axis_trig_ql_tready ;
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wire [32-1:0] s_axis_trig_intan_tdata ;
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wire s_axis_trig_intan_tvalid ;
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wire s_axis_trig_intan_tready ;
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wire [ 8-1:0] m_axis_eeg_tdata ;
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wire m_axis_eeg_tlast ;
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wire m_axis_eeg_tready ;
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wire m_axis_eeg_tvalid ;
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wire m_axis_eeg_ql_tready ;
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wire m_axis_eeg_intan_tready ;
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wire m_axis_ql_tfull ;
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wire [ 8-1:0] m_axis_ql_tdata ;
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wire [ 1-1:0] m_axis_ql_tkeep ;
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wire m_axis_ql_tlast ;
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wire m_axis_ql_tready ;
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wire m_axis_ql_tvalid ;
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wire m_axis_intan_tfull ;
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wire [ 8-1:0] m_axis_intan_tdata ;
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wire [ 1-1:0] m_axis_intan_tkeep ;
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wire m_axis_intan_tlast ;
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wire m_axis_intan_tready ;
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wire m_axis_intan_tvalid ;
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wire [ 4-1:0] debug_sig_sort ;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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run_time#
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(
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.CLK_PERIOD ( CLK_PERIOD )
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)
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u_run_time
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.pulse_ms ( pulse_ms ),
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.run_time_ms ( run_time_ms )
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);
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upload_config#
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(
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.CHANNLE_QTY ( CHANNLE_QTY ),
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.PRE_MSG_LEN ( PRE_MSG_LEN )
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)
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u_upload_config
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_addr ),
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.bram_clk ( bram_clk ),
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.bram_din ( bram_din ),
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.bram_dout ( bram_dout ),
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.bram_en ( bram_en ),
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.bram_rst ( bram_rst ),
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.bram_we ( bram_we ),
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.eeg_sel ( eeg_sel ),
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.protocol_sel ( protocol_sel ),
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.pre_message_array ( pre_message_array ),
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.pre_message_length ( pre_message_length ),
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.upload_round_qty_set ( upload_round_qty_set ),
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.ch_mapping2pc_array ( ch_mapping2pc_array ),
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.upload_ch_array ( upload_ch_array ),
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.reset_package_id ( reset_package_id ),
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.package_overtime_ms ( overtime_ms )
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);
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upload_sort#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.CHANNLE_QTY ( CHANNLE_QTY )
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)
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u_upload_sort
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.eeg_sel ( eeg_sel ),
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.protocol_sel ( protocol_sel ),
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.ch_mapping2pc_array ( ch_mapping2pc_array ),
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.upload_ch_array ( upload_ch_array ),
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//------------------------------------------ PL logic
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.s_axis_eeg16_tdata ( s_axis_eeg16_tdata ),
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.s_axis_eeg16_tlast ( s_axis_eeg16_tlast ),
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.s_axis_eeg16_tready ( s_axis_eeg16_tready ),
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.s_axis_eeg16_tvalid ( s_axis_eeg16_tvalid ),
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.s_axis_eeg24_tdata ( s_axis_eeg24_tdata ),
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.s_axis_eeg24_tlast ( s_axis_eeg24_tlast ),
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.s_axis_eeg24_tready ( s_axis_eeg24_tready ),
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.s_axis_eeg24_tvalid ( s_axis_eeg24_tvalid ),
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//------------------------------------------ PC logic
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.m_axis_eeg_tdata ( m_axis_eeg_tdata ),
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.m_axis_eeg_tlast ( m_axis_eeg_tlast ),
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.m_axis_eeg_tready ( m_axis_eeg_tready ),
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.m_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
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.debug_sig_sort ( debug_sig_sort )
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);
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upload_protocol_ql#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.PRE_MSG_LEN ( PRE_MSG_LEN )
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)
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u_upload_protocol_ql
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( protocol_sel ),
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.pulse_ms ( pulse_ms ),
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.run_time_ms ( run_time_ms ),
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.pre_message_array ( pre_message_array ),
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.pre_message_length ( pre_message_length ),
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.upload_round_qty_set ( upload_round_qty_set ),
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.reset_package_id ( reset_package_id ),
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.package_overtime_ms ( overtime_ms ),
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.s_axis_trigger_tdata ( s_axis_trig_ql_tdata ),
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.s_axis_trigger_tvalid ( s_axis_trig_ql_tvalid ),
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.s_axis_trigger_tready ( s_axis_trig_ql_tready ),
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.s_axis_eeg_tdata ( m_axis_eeg_tdata ),
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.s_axis_eeg_tlast ( m_axis_eeg_tlast ),
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.s_axis_eeg_tready ( m_axis_eeg_ql_tready ),
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.s_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
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.accel_data ( accel_data ),
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.m_axis_record_tfull ( m_axis_ql_tfull ),
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.m_axis_record_tdata ( m_axis_ql_tdata ),
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.m_axis_record_tkeep ( m_axis_ql_tkeep ),
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.m_axis_record_tlast ( m_axis_ql_tlast ),
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.m_axis_record_tready ( m_axis_ql_tready ),
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.m_axis_record_tvalid ( m_axis_ql_tvalid )
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);
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upload_protocol_intan#
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(
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.CLK_PERIOD ( CLK_PERIOD )
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)
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u_upload_protocol_intan
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( !protocol_sel ),
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.interrupt ( ),
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.pulse_ms ( pulse_ms ),
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.upload_round_qty_set ( upload_round_qty_set ),
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.reset_package_id ( reset_package_id ),
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.package_overtime_ms ( overtime_ms ),
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.s_axis_trigger_tdata ( s_axis_trig_intan_tdata ),
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.s_axis_trigger_tvalid ( s_axis_trig_intan_tvalid ),
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.s_axis_trigger_tready ( s_axis_trig_intan_tready ),
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.s_axis_eeg_tdata ( m_axis_eeg_tdata ),
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.s_axis_eeg_tlast ( m_axis_eeg_tlast ),
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.s_axis_eeg_tready ( m_axis_eeg_intan_tready),
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.s_axis_eeg_tvalid ( m_axis_eeg_tvalid ),
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.m_axis_record_tfull ( m_axis_intan_tfull ),
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.m_axis_record_tdata ( m_axis_intan_tdata ),
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.m_axis_record_tkeep ( m_axis_intan_tkeep ),
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.m_axis_record_tlast ( m_axis_intan_tlast ),
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.m_axis_record_tready ( m_axis_intan_tready ),
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.m_axis_record_tvalid ( m_axis_intan_tvalid )
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);
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign s_axis_trig_ql_tdata = s_axis_trigger_tdata;
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assign s_axis_trig_ql_tvalid = s_axis_trigger_tvalid;
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assign s_axis_trig_intan_tdata = s_axis_trigger_tdata;
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assign s_axis_trig_intan_tvalid = s_axis_trigger_tvalid;
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assign s_axis_trigger_tready = s_axis_trig_ql_tready || s_axis_trig_intan_tready;
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assign m_axis_eeg_tready = m_axis_eeg_ql_tready || m_axis_eeg_intan_tready;
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assign m_axis_record_tdata = (protocol_sel)? m_axis_ql_tdata : m_axis_intan_tdata;
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assign m_axis_record_tkeep = (protocol_sel)? m_axis_ql_tkeep : m_axis_intan_tkeep;
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assign m_axis_record_tlast = (protocol_sel)? m_axis_ql_tlast : m_axis_intan_tlast;
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assign m_axis_record_tvalid = (protocol_sel)? m_axis_ql_tvalid: m_axis_intan_tvalid;
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assign m_axis_ql_tfull = m_axis_record_tfull;
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assign m_axis_intan_tfull = m_axis_record_tfull;
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assign m_axis_ql_tready = m_axis_record_tready;
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assign m_axis_intan_tready = m_axis_record_tready;
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endmodule
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