89 lines
2.1 KiB
Verilog
89 lines
2.1 KiB
Verilog
`timescale 1ns/1ps
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module trans_timer_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 20; //ns
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg enable ;
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reg [32-1:0] update_period ;
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wire update ;
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wire trans ;
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#500
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@ ( posedge clk ) enable <= 1'b1;
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#1_000
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@ ( posedge clk ) enable <= 1'b0;
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#500
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@ ( posedge clk ) update_period <= (300)/20;
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@ ( posedge clk ) enable <= 1'b1;
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#1_000
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@ ( posedge clk ) enable <= 1'b0;
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#500
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@ ( posedge clk ) update_period <= (320)/20;
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@ ( posedge clk ) enable <= 1'b1;
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#1_000
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@ ( posedge clk ) enable <= 1'b0;
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#500
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@ ( posedge clk ) update_period <= (340)/20;
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@ ( posedge clk ) enable <= 1'b1;
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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enable <= 1'b0 ;
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update_period <= (160)/20;
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end
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endtask
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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trans_timer#
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(
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.CLK_PERIOD ( T_CLK ),
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.TRANS_PERIOD ( 160 )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( enable ),
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.update_period ( update_period ),
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.update ( update ),
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.trans ( trans )
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);
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endmodule |