453 lines
14 KiB
Verilog
453 lines
14 KiB
Verilog
`timescale 1 ns / 1 ps
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module rhs2116_top#
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(
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parameter VERSION = 32'h10000000 ,
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parameter CLK_PERIOD = 10 ,
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parameter SPI_CLK_DIV = 4 ,
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parameter SPI_DATA_WIDTH = 32 ,
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parameter SPI_TRANS_PERIOD = 1500 , //Unit: ns
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parameter CHIPSET_QTY = 4 ,
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parameter CH_OF_CHIPSET = 16 ,
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parameter REG_ADDR_STIM_POL = 8'd44 ,
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parameter REG_ADDR_POS_CUR = 8'd96 ,
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parameter REG_ADDR_NEG_CUR = 8'd64
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output interrupt ,
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//------------------------------------------ Trigger
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output [32-1:0] stim_event_code ,
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//------------------------------------------ FIFO: stim data input
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input [32-1:0] axi_str_txd_tdata ,
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input axi_str_txd_tlast ,
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output axi_str_txd_tready ,
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input axi_str_txd_tvalid ,
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//------------------------------------------ FIFO: record data output
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output [32-1:0] axi_str_rxd_tdata ,
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output axi_str_rxd_tlast ,
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input axi_str_rxd_tready ,
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output axi_str_rxd_tvalid ,
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//------------------------------------------ channel stim state
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output sw_enable ,
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output sw_data_sel ,
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output [64-1:0] sw_data_0 ,
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output [64-1:0] sw_data_1 ,
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input [64-1:0] sw_state ,
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//------------------------------------------ device
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output [CHIPSET_QTY-1:0] stim_en ,
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output [CHIPSET_QTY-1:0] cs ,
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output [CHIPSET_QTY-1:0] sclk ,
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output [CHIPSET_QTY-1:0] mosi ,
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input [CHIPSET_QTY-1:0] miso ,
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output [ 4-1:0] debug_sig
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);
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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//--------------------------------------------------------------------- config
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wire [32-1:0] update_period ;
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wire enable_timer ;
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wire dds_by_ps ;
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wire dds_aclken_ps ;
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wire dds_aresetn_ps ;
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wire dds_aclken_pl ;
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wire dds_aresetn_pl ;
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wire dds_aclken ;
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wire dds_aresetn ;
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wire [16* 8*CHIPSET_QTY-1:0] stim_trim_p_array_array ;
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wire [16* 8*CHIPSET_QTY-1:0] stim_trim_n_array_array ;
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wire [16* 8-1:0] stim_trim_p_array[0:CHIPSET_QTY-1] ;
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wire [16* 8-1:0] stim_trim_n_array[0:CHIPSET_QTY-1] ;
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wire phase_enable ;
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wire [32*16-1:0] phase_inc_array ;
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wire [32*16-1:0] phase_off_array ;
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wire [16*9-1:0] sine_wave_array ;
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//--------------------------------------------------------------------- spi communication
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wire [ 1*CHIPSET_QTY-1:0] spi_cmd_valid_array ;
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wire [32*CHIPSET_QTY-1:0] spi_cmd_data_array ;
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wire [ 1*CHIPSET_QTY-1:0] spi_cmd_ready_array ;
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wire [ 1*CHIPSET_QTY-1:0] spi_res_en_array ;
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wire [32*CHIPSET_QTY-1:0] spi_res_array ;
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wire spi_cmd_valid[0:CHIPSET_QTY-1] ;
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wire [32-1:0] spi_cmd_data[0:CHIPSET_QTY-1] ;
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wire spi_cmd_ready[0:CHIPSET_QTY-1] ;
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wire spi_res_en[0:CHIPSET_QTY-1] ;
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wire [32-1:0] spi_res[0:CHIPSET_QTY-1] ;
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//--------------------------------------------------------------------- transmit timer
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wire trans_round ;
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wire trans_pulse ;
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//--------------------------------------------------------------------- stim stream
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wire [32*CHIPSET_QTY-1:0] axis_ctrl_tdata_array ;
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wire [ 1*CHIPSET_QTY-1:0] axis_ctrl_tlast_array ;
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wire [ 1*CHIPSET_QTY-1:0] axis_ctrl_tready_array ;
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wire [ 1*CHIPSET_QTY-1:0] axis_ctrl_tvalid_array ;
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wire [32-1:0] axis_ctrl_tdata[0:CHIPSET_QTY-1] ;
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wire axis_ctrl_tlast[0:CHIPSET_QTY-1] ;
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wire axis_ctrl_tready[0:CHIPSET_QTY-1] ;
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wire axis_ctrl_tvalid[0:CHIPSET_QTY-1] ;
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wire [16-1:0] record_ch_qty ;
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wire [32-1:0] m_axi_trans_tdata[0:CHIPSET_QTY-1] ;
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wire m_axi_trans_tlast[0:CHIPSET_QTY-1] ;
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wire m_axi_trans_tready[0:CHIPSET_QTY-1] ;
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wire m_axi_trans_tvalid[0:CHIPSET_QTY-1] ;
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//--------------------------------------------------------------------- conver result
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wire [32-1:0] cnv_res_tdata[0:CHIPSET_QTY-1] ;
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wire cnv_res_tlast[0:CHIPSET_QTY-1] ;
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wire cnv_res_tready[0:CHIPSET_QTY-1] ;
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wire cnv_res_tvalid[0:CHIPSET_QTY-1] ;
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wire [32*CHIPSET_QTY-1:0] cnv_res_tdata_array ;
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wire [ CHIPSET_QTY-1:0] cnv_res_tlast_array ;
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wire [ CHIPSET_QTY-1:0] cnv_res_tready_array ;
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wire [ CHIPSET_QTY-1:0] cnv_res_tvalid_array ;
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//--------------------------------------------------------------------- Compliance Monitor
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wire [ 16-1:0] monitor_data[0:CHIPSET_QTY-1] ;
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wire [16*CHIPSET_QTY-1:0] monitor_data_array ;
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wire [ 64-1:0] stim_monitor_rt ;
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wire [ 64-1:0] stim_monitor_latch ;
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wire [ 16-1:0] stim_state[0:CHIPSET_QTY-1] ;
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wire [ 32-1:0] stim_stage_code[0:CHIPSET_QTY-1] ;
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wire [32*CHIPSET_QTY-1:0] event_in_arrary ;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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transmit_config#
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(
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.CHIPSET_QTY ( CHIPSET_QTY )
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)
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u_transmit_config
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_addr ),
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.bram_clk ( bram_clk ),
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.bram_din ( bram_din ),
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.bram_dout ( bram_dout ),
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.bram_en ( bram_en ),
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.bram_rst ( bram_rst ),
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.bram_we ( bram_we ),
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.stim_en ( stim_en ),
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.update_period ( update_period ),
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.enable_timer ( enable_timer ),
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.dds_by_ps ( dds_by_ps ),
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.dds_aclken ( dds_aclken_ps ),
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.dds_aresetn ( dds_aresetn_ps ),
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.sw_enable ( sw_enable ),
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.sw_data_sel ( sw_data_sel ),
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.sw_data_0 ( sw_data_0 ),
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.sw_state ( sw_state ),
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.stim_trim_p_array_array( stim_trim_p_array_array),
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.stim_trim_n_array_array( stim_trim_n_array_array),
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.phase_enable ( phase_enable ),
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.phase_inc_array ( phase_inc_array ),
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.phase_off_array ( phase_off_array ),
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.stim_monitor_rt ( stim_monitor_rt ),
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.stim_monitor_latch ( stim_monitor_latch ),
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.spi_cmd_valid_array ( spi_cmd_valid_array ),
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.spi_cmd_data_array ( spi_cmd_data_array ),
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.spi_cmd_ready_array ( spi_cmd_ready_array ),
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.spi_res_en_array ( spi_res_en_array ),
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.spi_res_array ( spi_res_array )
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);
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trans_timer#
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(
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.CLK_PERIOD ( CLK_PERIOD ),
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.SPI_TRANS_PERIOD ( SPI_TRANS_PERIOD )
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)
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u_trans_timer
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.update_period ( update_period ),
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.enable ( axi_str_txd_tvalid ), //enable_timer
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.trans_round ( trans_round ),
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.trans_pulse ( trans_pulse )
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);
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sine_gen u_sine_wave_gen
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.phase_enable ( phase_enable ),
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.phase_inc_array ( phase_inc_array ),
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.phase_off_array ( phase_off_array ),
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.dds_aclken ( dds_aclken ),
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.dds_aresetn ( dds_aresetn ),
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.update ( trans_round ),
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.sine_wave_array ( sine_wave_array )
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);
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trans_distribute u_trans_distribute
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trans_round ( trans_round ),
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.s_axi_rx_tdata ( axi_str_txd_tdata ),
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.s_axi_rx_tlast ( axi_str_txd_tlast ),
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.s_axi_rx_tready ( axi_str_txd_tready ),
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.s_axi_rx_tvalid ( axi_str_txd_tvalid ),
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.record_ch_qty ( record_ch_qty ),
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.dds_aclken ( dds_aclken_pl ),
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.dds_aresetn ( dds_aresetn_pl ),
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.m_axi_tx_aresetn ( rst_n ),
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.m_axi_tx_tdata_array ( axis_ctrl_tdata_array ),
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.m_axi_tx_tlast_array ( axis_ctrl_tlast_array ),
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.m_axi_tx_tready_array ( axis_ctrl_tready_array),
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.m_axi_tx_tvalid_array ( axis_ctrl_tvalid_array)
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);
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : transmit_arrange
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trans_arrange#
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(
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.REG_ADDR_STIM_POL ( 8'd44 ),
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.REG_ADDR_POS_CUR ( 8'd64 ),
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.REG_ADDR_NEG_CUR ( 8'd96 )
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)
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u_trans_arrange
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.stim_trim_p_array ( stim_trim_p_array[i] ),
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.stim_trim_n_array ( stim_trim_n_array[i] ),
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.sine_wave_array ( sine_wave_array ),
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.trans_round ( trans_round ),
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//--------------------------------------------------input
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.s_axi_cmd_tdata ( axis_ctrl_tdata[i] ),
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.s_axi_cmd_tlast ( axis_ctrl_tlast[i] ),
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.s_axi_cmd_tready ( axis_ctrl_tready[i] ),
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.s_axi_cmd_tvalid ( axis_ctrl_tvalid[i] ),
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//--------------------------------------------------output
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.m_axi_trans_tdata ( m_axi_trans_tdata[i] ),
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.m_axi_trans_tlast ( m_axi_trans_tlast[i] ),
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.m_axi_trans_tready ( m_axi_trans_tready[i] ),
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.m_axi_trans_tvalid ( m_axi_trans_tvalid[i] )
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);
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : trans_if
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transmit_if#
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(
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.SPI_CLK_DIV ( SPI_CLK_DIV ),
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.SPI_DATA_WIDTH ( SPI_DATA_WIDTH ),
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.CH_OF_CHIPSET ( CH_OF_CHIPSET ),
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.CMD_CONVERT ( 2'b00 ),
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.CMD_EXTEND ( 2'b01 ),
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.CMD_WRITE ( 2'b10 ),
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.CMD_READ ( 2'b11 ),
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.REG_ADDR_MONITOR ( 8'd40 )
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)
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u_transmit_if
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trans_round ( trans_round ),
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.trans_pulse ( trans_pulse ),
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//------------------------------------------ spi direct communication
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.spi_cmd_valid ( spi_cmd_valid[i] ),
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.spi_cmd_data ( spi_cmd_data[i] ),
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.spi_cmd_ready ( spi_cmd_ready[i] ),
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.spi_res_en ( spi_res_en[i] ),
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.spi_res ( spi_res[i] ),
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//------------------------------------------ cmd stream
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.s_axis_trans_tdata ( m_axi_trans_tdata[i] ),
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.s_axis_trans_tlast ( m_axi_trans_tlast[i] ),
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.s_axis_trans_tready ( m_axi_trans_tready[i] ),
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.s_axis_trans_tvalid ( m_axi_trans_tvalid[i] ),
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//------------------------------------------ record stream
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.cnv_res_tdata ( cnv_res_tdata[i] ),
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.cnv_res_tlast ( cnv_res_tlast[i] ),
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.cnv_res_tready ( cnv_res_tready[i] ),
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.cnv_res_tvalid ( cnv_res_tvalid[i] ),
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//------------------------------------------ monitor
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.monitor_data_en ( ),
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.monitor_data ( monitor_data[i] ),
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.stim_state ( stim_state[i] ),
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.stim_stage_code ( stim_stage_code[i] ),
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//------------------------------------------ device spi
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.cs ( cs[i] ),
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.sclk ( sclk[i] ),
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.mosi ( mosi[i] ),
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.miso ( miso[i] )
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);
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end
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endgenerate
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cnv_res_collect#
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(
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.CHIPSET_QTY ( CHIPSET_QTY ),
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.CH_OF_CHIPSET ( CH_OF_CHIPSET )
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)
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u_cnv_res_collect
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trans_round ( trans_round ),
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.record_ch_qty ( record_ch_qty ),
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.cnv_res_tdata_array ( cnv_res_tdata_array ),
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.cnv_res_tlast_array ( cnv_res_tlast_array ),
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.cnv_res_tready_array ( cnv_res_tready_array ),
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.cnv_res_tvalid_array ( cnv_res_tvalid_array ),
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.m_axis_eeg_tdata ( axi_str_rxd_tdata ),
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.m_axis_eeg_tlast ( axi_str_rxd_tlast ),
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.m_axis_eeg_tready ( axi_str_rxd_tready ),
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.m_axis_eeg_tvalid ( axi_str_rxd_tvalid )
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);
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stim_event_collect#
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(
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.CHIPSET_QTY ( CHIPSET_QTY )
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)
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u_stim_event_collect
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.event_in_arrary ( event_in_arrary ),
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.event_out ( stim_event_code )
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);
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stim_monitor#
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(
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.CLK_PERIOD ( CLK_PERIOD )
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)
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u_stim_monitor
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.stim_monitor_in ( monitor_data_array ),
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.stim_monitor_rt ( stim_monitor_rt ),
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.stim_monitor_latch ( stim_monitor_latch )
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);
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign dds_aclken = dds_by_ps? dds_aclken_ps :dds_aclken_pl;
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assign dds_aresetn = dds_by_ps? dds_aresetn_ps:dds_aresetn_pl;
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
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assign spi_cmd_ready_array[i] = spi_cmd_ready[i];
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assign spi_res_en_array[i] = spi_res_en[i];
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assign spi_res_array[32*i+31 : 32*i] = spi_res[i];
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assign axis_ctrl_tready_array[i] = axis_ctrl_tready[i];
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assign monitor_data_array[16*i+15 : 16*i] = monitor_data[i];
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assign cnv_res_tdata_array[32*i+31 : 32*i] = cnv_res_tdata[i];
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assign cnv_res_tlast_array[i] = cnv_res_tlast[i];
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assign cnv_res_tvalid_array[i] = cnv_res_tvalid[i];
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assign sw_data_1[16*i+15 : 16*i] = ~stim_state[i];
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assign event_in_arrary[32*i+31 : 32*i] = stim_stage_code[i];
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
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assign spi_cmd_data[i] = spi_cmd_data_array[32*i+31 : 32*i];
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assign spi_cmd_valid[i] = spi_cmd_valid_array[i];
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assign axis_ctrl_tdata[i] = axis_ctrl_tdata_array[32*i+31 : 32*i];
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assign axis_ctrl_tlast[i] = axis_ctrl_tlast_array[i];
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assign axis_ctrl_tvalid[i] = axis_ctrl_tvalid_array[i];
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assign cnv_res_tready[i] = cnv_res_tready_array[i];
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assign stim_trim_p_array[i] = stim_trim_p_array_array[16*8*i+16*8-1: 16*8*i];
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assign stim_trim_n_array[i] = stim_trim_n_array_array[16*8*i+16*8-1: 16*8*i];
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end
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endgenerate
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assign interrupt = 1'b0;
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assign debug_sig[0] = cs[3];
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assign debug_sig[1] = sclk[3];
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assign debug_sig[2] = mosi[3];
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assign debug_sig[3] = miso[3];
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endmodule
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