323 lines
29 KiB
Plaintext
323 lines
29 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Sun Aug 4 13:44:41 2024
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| Host : 840-5CG14025H4 running 64-bit major release (build 9200)
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| Command : report_clock_utilization -file c64pro_top_clock_utilization_routed.rpt
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| Design : c64pro_top
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| Device : 7z010-clg400
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| Speed File : -2 PRODUCTION 1.12 2019-11-22
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| Design State : Routed
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Global Clock Resources
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3. Global Clock Source Details
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4. Clock Regions: Key Resource Utilization
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5. Clock Regions : Global Clock Summary
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6. Device Cell Placement Summary for Global Clock g0
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7. Device Cell Placement Summary for Global Clock g1
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8. Device Cell Placement Summary for Global Clock g2
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9. Device Cell Placement Summary for Global Clock g3
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10. Device Cell Placement Summary for Global Clock g4
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11. Clock Region Cell Placement per Global Clock: Region X0Y0
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12. Clock Region Cell Placement per Global Clock: Region X1Y0
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13. Clock Region Cell Placement per Global Clock: Region X0Y1
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14. Clock Region Cell Placement per Global Clock: Region X1Y1
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1. Clock Primitive Utilization
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------------------------------
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+----------+------+-----------+-----+--------------+--------+
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| Type | Used | Available | LOC | Clock Region | Pblock |
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+----------+------+-----------+-----+--------------+--------+
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| BUFGCTRL | 5 | 32 | 0 | 0 | 0 |
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| BUFH | 0 | 48 | 0 | 0 | 0 |
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| BUFIO | 0 | 8 | 0 | 0 | 0 |
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| BUFMR | 0 | 4 | 0 | 0 | 0 |
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| BUFR | 0 | 8 | 0 | 0 | 0 |
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| MMCM | 0 | 2 | 0 | 0 | 0 |
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| PLL | 0 | 2 | 0 | 0 | 0 |
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+----------+------+-----------+-----+--------------+--------+
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2. Global Clock Resources
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-------------------------
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+
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| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+
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| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 4 | 18993 | 0 | 10.000 | clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 2 | 32 | 0 | | | n_0_6087_BUFG_inst/O | n_0_6087_BUFG |
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| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 2 | 32 | 0 | | | n_1_6243_BUFG_inst/O | n_1_6243_BUFG |
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| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 2 | 32 | 0 | | | n_2_6399_BUFG_inst/O | n_2_6399_BUFG |
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| g4 | src4 | BUFG/O | None | BUFGCTRL_X0Y4 | n/a | 1 | 32 | 0 | | | n_3_6555_BUFG_inst/O | n_3_6555_BUFG |
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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3. Global Clock Source Details
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------------------------------
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+-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+
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| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+
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| src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y1 | 1 | 0 | 10.000 | clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] |
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| src1 | g1 | LUT2/O | None | SLICE_X22Y45 | X1Y0 | 1 | 0 | | | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/n_0_6087_BUFG_inst_i_1/O | u_pl_top/u_rhs2116_top/trans_if[0].u_transmit_if/n_0_6087_BUFG_inst_n_1 |
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| src2 | g2 | LUT2/O | None | SLICE_X22Y46 | X1Y0 | 1 | 0 | | | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/n_1_6243_BUFG_inst_i_1/O | u_pl_top/u_rhs2116_top/trans_if[1].u_transmit_if/n_1_6243_BUFG_inst_n_2 |
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| src3 | g3 | LUT2/O | None | SLICE_X22Y45 | X1Y0 | 1 | 0 | | | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/n_2_6399_BUFG_inst_i_1/O | u_pl_top/u_rhs2116_top/trans_if[2].u_transmit_if/n_2_6399_BUFG_inst_n_3 |
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| src4 | g4 | LUT2/O | None | SLICE_X22Y46 | X1Y0 | 1 | 0 | | | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/n_3_6555_BUFG_inst_i_1/O | u_pl_top/u_rhs2116_top/trans_if[3].u_transmit_if/n_3_6555_BUFG_inst_n_4 |
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+-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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4. Clock Regions: Key Resource Utilization
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------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5201 | 1100 | 1949 | 400 | 0 | 20 | 7 | 10 | 0 | 20 |
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| X1Y0 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4690 | 1100 | 1540 | 350 | 0 | 40 | 17 | 20 | 0 | 20 |
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| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4341 | 1100 | 1603 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y1 | 5 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4389 | 1100 | 1420 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* Global Clock column represents track count; while other columns represents cell counts
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5. Clock Regions : Global Clock Summary
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---------------------------------------
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All Modules
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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6. Device Cell Placement Summary for Global Clock g0
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----------------------------------------------------
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+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+
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| g0 | BUFG/O | n/a | clk_fpga_0 | 10.000 | {0.000 5.000} | 18878 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-------+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+-------+-------+-----------------------+
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| Y1 | 4351 | 4400 | 0 |
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| Y0 | 5306 | 4821 | 0 |
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+----+-------+-------+-----------------------+
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7. Device Cell Placement Summary for Global Clock g1
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----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| g1 | BUFG/O | n/a | | | | 32 | 0 | 0 | 0 | n_0_6087_BUFG |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+-----+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+----+-----+-----------------------+
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| Y1 | 0 | 6 | 0 |
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| Y0 | 0 | 26 | 0 |
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+----+----+-----+-----------------------+
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8. Device Cell Placement Summary for Global Clock g2
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----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| g2 | BUFG/O | n/a | | | | 32 | 0 | 0 | 0 | n_1_6243_BUFG |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+-----+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+----+-----+-----------------------+
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| Y1 | 0 | 27 | 0 |
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| Y0 | 0 | 5 | 0 |
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+----+----+-----+-----------------------+
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9. Device Cell Placement Summary for Global Clock g3
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----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| g3 | BUFG/O | n/a | | | | 32 | 0 | 0 | 0 | n_2_6399_BUFG |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+-----+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+----+-----+-----------------------+
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| Y1 | 0 | 14 | 0 |
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| Y0 | 0 | 18 | 0 |
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+----+----+-----+-----------------------+
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10. Device Cell Placement Summary for Global Clock g4
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-----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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| g4 | BUFG/O | n/a | | | | 32 | 0 | 0 | 0 | n_3_6555_BUFG |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+-----+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+----+-----+-----------------------+
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| Y1 | 0 | 32 | 0 |
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| Y0 | 0 | 0 | - |
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+----+----+-----+-----------------------+
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11. Clock Region Cell Placement per Global Clock: Region X0Y0
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| g0 | n/a | BUFG/O | None | 5306 | 0 | 5201 | 97 | 7 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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12. Clock Region Cell Placement per Global Clock: Region X1Y0
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| g0 | n/a | BUFG/O | None | 4821 | 0 | 4690 | 112 | 17 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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| g1 | n/a | BUFG/O | None | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_0_6087_BUFG |
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| g2 | n/a | BUFG/O | None | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_1_6243_BUFG |
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| g3 | n/a | BUFG/O | None | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_2_6399_BUFG |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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13. Clock Region Cell Placement per Global Clock: Region X0Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| g0 | n/a | BUFG/O | None | 4351 | 0 | 4341 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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14. Clock Region Cell Placement per Global Clock: Region X1Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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| g0 | n/a | BUFG/O | None | 4400 | 0 | 4389 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 |
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| g1 | n/a | BUFG/O | None | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_0_6087_BUFG |
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| g2 | n/a | BUFG/O | None | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_1_6243_BUFG |
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| g3 | n/a | BUFG/O | None | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_2_6399_BUFG |
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| g4 | n/a | BUFG/O | None | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n_3_6555_BUFG |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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# Location of BUFG Primitives
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set_property LOC BUFGCTRL_X0Y0 [get_cells u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG]
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set_property LOC BUFGCTRL_X0Y4 [get_cells n_3_6555_BUFG_inst]
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set_property LOC BUFGCTRL_X0Y3 [get_cells n_2_6399_BUFG_inst]
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set_property LOC BUFGCTRL_X0Y2 [get_cells n_1_6243_BUFG_inst]
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set_property LOC BUFGCTRL_X0Y1 [get_cells n_0_6087_BUFG_inst]
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# Location of IO Primitives which is load of clock spine
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# Location of clock ports
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# Clock net "u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0" driven by instance "u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y0"
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#startgroup
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create_pblock {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}
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add_cells_to_pblock [get_pblocks {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}]]]
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resize_pblock [get_pblocks {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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# Clock net "n_3_6555_BUFG" driven by instance "n_3_6555_BUFG_inst" located at site "BUFGCTRL_X0Y4"
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#startgroup
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create_pblock {CLKAG_n_3_6555_BUFG}
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add_cells_to_pblock [get_pblocks {CLKAG_n_3_6555_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {n_3_6555_BUFG}]]]
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resize_pblock [get_pblocks {CLKAG_n_3_6555_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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# Clock net "n_2_6399_BUFG" driven by instance "n_2_6399_BUFG_inst" located at site "BUFGCTRL_X0Y3"
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#startgroup
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create_pblock {CLKAG_n_2_6399_BUFG}
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add_cells_to_pblock [get_pblocks {CLKAG_n_2_6399_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {n_2_6399_BUFG}]]]
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resize_pblock [get_pblocks {CLKAG_n_2_6399_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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# Clock net "n_1_6243_BUFG" driven by instance "n_1_6243_BUFG_inst" located at site "BUFGCTRL_X0Y2"
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#startgroup
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create_pblock {CLKAG_n_1_6243_BUFG}
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add_cells_to_pblock [get_pblocks {CLKAG_n_1_6243_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {n_1_6243_BUFG}]]]
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resize_pblock [get_pblocks {CLKAG_n_1_6243_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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# Clock net "n_0_6087_BUFG" driven by instance "n_0_6087_BUFG_inst" located at site "BUFGCTRL_X0Y1"
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#startgroup
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create_pblock {CLKAG_n_0_6087_BUFG}
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add_cells_to_pblock [get_pblocks {CLKAG_n_0_6087_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {n_0_6087_BUFG}]]]
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resize_pblock [get_pblocks {CLKAG_n_0_6087_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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