17 lines
1.1 KiB
Tcl
17 lines
1.1 KiB
Tcl
# This file is automatically generated.
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# It contains project source information necessary for synthesis and implementation.
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# IP: D:/wlb_files/VivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci
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# IP: The module: 'dds_stim_16ch' is the root of the design. Do not add the DONT_TOUCH constraint.
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# XDC: d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc
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# XDC: The top module name and the constraint reference have the same name: 'dds_stim_16ch'. Do not add the DONT_TOUCH constraint.
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set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
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# IP: D:/wlb_files/VivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci
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# IP: The module: 'dds_stim_16ch' is the root of the design. Do not add the DONT_TOUCH constraint.
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# XDC: d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc
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# XDC: The top module name and the constraint reference have the same name: 'dds_stim_16ch'. Do not add the DONT_TOUCH constraint.
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#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
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