2588 lines
324 KiB
Plaintext
2588 lines
324 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Wed Sep 2 11:59:32 2026
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# Process ID: 35916
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# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v4
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent20564 D:\Project\spinal_stim\pl\spinal_stim_v4\c64_pro.xpr
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# Log file: D:/Project/spinal_stim/pl/spinal_stim_v4/vivado.log
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# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v4\vivado.jou
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# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
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#-----------------------------------------------------------
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start_gui
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open_project D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.3 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.3/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
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open_project: Time (s): cpu = 00:00:59 ; elapsed = 00:00:34 . Memory (MB): peak = 2695.895 ; gain = 564.992
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open_hw_manager
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connect_hw_server -allow_non_jtag
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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****** Xilinx hw_server v2023.1
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**** Build date : May 7 2023 at 15:26:57
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
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INFO: [Labtools 27-3417] Launching cs_server...
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INFO: [Labtools 27-2221] Launch Output:
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******** Xilinx cs_server v2023.1.0
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****** Build date : Apr 10 2023-23:59:24
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**** Build number : 2023.1.1681142364
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** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
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connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2756.289 ; gain = 0.000
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open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210251584078.
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Check cable connectivity and that the target board is powered up then
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use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
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ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
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WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
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close_hw_manager
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open_hw_manager
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connect_hw_server -allow_non_jtag
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
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INFO: [Labtools 27-3417] Launching cs_server...
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INFO: [Labtools 27-2221] Launch Output:
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******** Xilinx cs_server v2023.1.0
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****** Build date : Apr 10 2023-23:59:24
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**** Build number : 2023.1.1681142364
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** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
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open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
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set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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current_hw_device [get_hw_devices xc7z020_1]
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refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq8'hXX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:16:40
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:16:40
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 3091.988 ; gain = 29.730
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:17:01
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:18:12
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 3091.988 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tlast -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:19:02
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:19:02
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 3091.988 ; gain = 0.000
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set_property CONTROL.TRIGGER_POSITION 1000 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:19:37
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:19:37
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3393.539 ; gain = 301.551
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:26:21
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:26:21
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3951.500 ; gain = 0.000
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 13:29:28
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 13:29:28
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3951.500 ; gain = 0.000
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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close_hw_manager
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launch_simulation
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Command: launch_simulation
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INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
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WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
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INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
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INFO: [USF-XSim-7] Finding pre-compiled libraries...
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INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:24 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '24' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:01:03 ; elapsed = 00:01:32 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/clk}} {{/pl_top_tb/DUT/u_eeg_emg_upload/rst_n}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/diff_pkt_data_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/emg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/stop_sample}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_data_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_fifo_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en_dly}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_en_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_data}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/msg_crc}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16_out}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc_vld}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rst}}
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|
restart
|
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INFO: [Wavedata 42-604] Simulation restarted
|
|
run 1 ms
|
|
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 3951.500 ; gain = 0.000
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run 10 ms
|
|
run: Time (s): cpu = 00:00:29 ; elapsed = 00:02:23 . Memory (MB): peak = 3951.500 ; gain = 0.000
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save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
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|
close_sim
|
|
INFO: xsimkernel Simulation Memory Usage: 30492 KB (Peak: 30492 KB), Simulation CPU Usage: 155390 ms
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
Command: launch_simulation
|
|
INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
|
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:30 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '30' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
|
|
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
|
|
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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|
There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
xsim: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 3951.500 ; gain = 0.000
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|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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|
launch_simulation: Time (s): cpu = 00:00:52 ; elapsed = 00:01:26 . Memory (MB): peak = 3951.500 ; gain = 0.000
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|
restart
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|
INFO: [Wavedata 42-604] Simulation restarted
|
|
run 10 ms
|
|
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
run: Time (s): cpu = 00:00:45 ; elapsed = 00:02:18 . Memory (MB): peak = 3951.500 ; gain = 0.000
|
|
current_wave_config {pl_top_tb_behav.wcfg}
|
|
pl_top_tb_behav.wcfg
|
|
add_wave {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/clk}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/rst_n}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/trans_round}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tdata_array}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tlast_array}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tready_array}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tvalid_array}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/axi_str_rxd_tdata}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/axi_str_rxd_tlast}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/axi_str_rxd_tready}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/axi_str_rxd_tvalid}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cstate}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/nstate}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tdata}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tlast}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tready}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tvalid}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tdata_r}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/cnv_res_tvalid_r}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/scan_cnt}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/round_end}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/CLK_PERIOD}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/CHIPSET_QTY}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/CH_OF_CHIPSET}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/TIME_OUT_MS}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/IDLE}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/READY_ST}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/SCAN_ST}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/CLKS}} {{/pl_top_tb/DUT/u0_eeg_top/u_eeg_upload/TIME_OUT_CLKS}}
|
|
restart
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|
run 10 ms
|
|
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
|
|
Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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|
run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 3951.500 ; gain = 0.000
|
|
current_wave_config {pl_top_tb_behav.wcfg}
|
|
pl_top_tb_behav.wcfg
|
|
add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/clk}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/rst_n}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/enable}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/interrupt}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/pulse_ms}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/run_time_ms}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/pre_message_array}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/pre_message_length}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_round_qty_set}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/reset_package_id}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/package_overtime_ms}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_trigger_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_trigger_tvalid}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_trigger_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/accel_data}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tfull}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tkeep}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tvalid}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/cstate}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/nstate}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/overtime_ms}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/package_id}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/pre_message}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/trigger_word}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/trigger_byte}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/msg_crc}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_round_qty}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_bytes_cnt}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_bytes_cnt_add1}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_rounds_cnt}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_record_bytes_cnt}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/crc16_out}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/crc16}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_addl}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/byte_cnt}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_break}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/upload_disable}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/debug_sig_sort}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/CLK_PERIOD}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/CHANNLE_QTY}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/PRE_MSG_LEN}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_IDLE}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_MSG_HEAD}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_WAIT}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_READ_TRIGGER}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_MSG_TRIGGER}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_MSG_RECORD}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_MSG_CRC}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ST_ADDITIONAL}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/ADDL_NUM}}
|
|
restart
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|
run 10 ms
|
|
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:01:14 ; elapsed = 00:02:16 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/clk}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/rst_n}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_addr}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_clk}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_din}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_dout}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_en}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_rst}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_we}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/eeg_sel}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/protocol_sel}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/pre_message_array}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/ch_mapping2pc_array}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/upload_ch_array}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/upload_round_qty_set}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/pre_message_length}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/reset_package_id}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/package_overtime_ms}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/test_data}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_wr_valid}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/bram_rd_valid}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/pre_message}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/ch_mapping2pc}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/upload_ch}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/upload_ch_array_w}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/n}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/CHANNLE_QTY}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/PRE_MSG_LEN}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_TEST_RO}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_TEST_RW}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_SEL}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_ROUNDS_QTY}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_PRE_MSG_LTH}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_RESET_PACKAGE_ID}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_PACKAGE_OVERTIME}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_MESSAGE_END}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_PRE_MSG_START}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_PRE_MSG_MASK}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_CH_MAP_START}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_CH_MAP_MASK}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_UPLOAD_CH_START}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/BRAM_ADDR_UPLOAD_CH_MASK}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_config/N}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:35 ; elapsed = 00:01:17 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
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close_sim
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INFO: xsimkernel Simulation Memory Usage: 30920 KB (Peak: 30920 KB), Simulation CPU Usage: 364718 ms
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INFO: [Simtcl 6-16] Simulation closed
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launch_simulation
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Command: launch_simulation
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INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
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WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
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INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
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INFO: [USF-XSim-7] Finding pre-compiled libraries...
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INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
|
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INFO: [USF-XSim-3] XSim::Elaborate design
|
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:28 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '29' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:01:02 ; elapsed = 00:01:35 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/clk}} {{/pl_top_tb/DUT/u_eeg_emg_upload/rst_n}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/diff_pkt_data_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/emg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/stop_sample}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_data_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_fifo_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en_dly}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_en_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_data}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/msg_crc}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16_out}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc16}} {{/pl_top_tb/DUT/u_eeg_emg_upload/crc_vld}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rst}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:41 ; elapsed = 00:02:10 . Memory (MB): peak = 3951.500 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tkeep}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/m_axis_record_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_protocol_ql/s_axis_eeg_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tvalid}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eegY_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eegY_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eegY_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eegY_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
|
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eeg24_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eeg24_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eeg24_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eeg24_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/eeg_sel}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/protocol_sel}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eegX_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eegX_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eegX_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/s_axis_eegX_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/record_rx}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:36 ; elapsed = 00:01:23 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/ch_pc}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/record_tx}}
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restart
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|
run 10 ms
|
|
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
|
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 3951.500 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tready}} {{/pl_top_tb/DUT/u0_upload_top/u_upload_sort/m_axis_eeg_tvalid}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:37 ; elapsed = 00:02:12 . Memory (MB): peak = 3951.500 ; gain = 0.000
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tfull}} {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tdata}} {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tkeep}} {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tlast}} {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tready}} {{/pl_top_tb/DUT/u0_upload_top/m_axis_record_tvalid}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_eeg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/m_axis_emg_tvalid}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/diff_pkt_data_sel}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_sel}}
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_send_package_num}} {{/pl_top_tb/DUT/u_eeg_emg_upload/emg_send_package_num}}
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save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
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close_sim
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INFO: xsimkernel Simulation Memory Usage: 30984 KB (Peak: 30984 KB), Simulation CPU Usage: 492327 ms
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INFO: [Simtcl 6-16] Simulation closed
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launch_simulation
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Command: launch_simulation
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INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
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WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
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INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
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INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
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INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
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INFO: [USF-XSim-7] Finding pre-compiled libraries...
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INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
|
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'glbl' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/glbl.v:6]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 4085.598 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:23 . Memory (MB): peak = 4085.598 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '23' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4085.598 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:49 ; elapsed = 00:01:19 . Memory (MB): peak = 4085.598 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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INFO: [Common 17-41] Interrupt caught. Command should exit soon.
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run: Time (s): cpu = 00:00:25 ; elapsed = 00:00:59 . Memory (MB): peak = 4085.598 ; gain = 0.000
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INFO: [Common 17-344] 'run' was cancelled
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current_wave_config {pl_top_tb_behav.wcfg}
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pl_top_tb_behav.wcfg
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add_wave {{/pl_top_tb/DUT/u_eeg_emg_upload/stop_sample}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_data_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_fifo_tdata}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_emg_rd_en_dly}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_en_cnt}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rd_data}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/axis_eeg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tdata_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tvalid_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/eeg_emg_tlast_tmp}} {{/pl_top_tb/DUT/u_eeg_emg_upload/fifo_rst}}
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:00:42 ; elapsed = 00:02:10 . Memory (MB): peak = 4085.598 ; gain = 0.000
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open_hw_manager
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connect_hw_server -allow_non_jtag
|
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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****** Xilinx hw_server v2023.1
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**** Build date : May 7 2023 at 15:26:57
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
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INFO: [Labtools 27-3417] Launching cs_server...
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INFO: [Labtools 27-2221] Launch Output:
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******** Xilinx cs_server v2023.1.0
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****** Build date : Apr 10 2023-23:59:24
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|
**** Build number : 2023.1.1681142364
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** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
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connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 4086.809 ; gain = 0.000
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open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251584078
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set_property PROGRAM.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.bit} [get_hw_devices xc7z020_1]
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set_property PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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set_property FULL_PROBES.FILE {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.runs/impl_1/c64pro_top.ltx} [get_hw_devices xc7z020_1]
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|
current_hw_device [get_hw_devices xc7z020_1]
|
|
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
|
|
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
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INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s).
|
|
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property CONTROL.TRIGGER_POSITION 200 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 16:39:19
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|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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|
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 16:39:19
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|
INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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|
display_hw_ila_data: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4086.809 ; gain = 0.000
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set_property CONTROL.TRIGGER_POSITION 1000 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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|
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 16:39:54
|
|
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
|
|
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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|
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 16:39:54
|
|
INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
|
|
display_hw_ila_data: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4086.809 ; gain = 0.000
|
|
save_wave_config {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg}
|
|
close_sim
|
|
INFO: xsimkernel Simulation Memory Usage: 23140 KB (Peak: 23140 KB), Simulation CPU Usage: 188031 ms
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|
launch_simulation
|
|
Command: launch_simulation
|
|
INFO: [Vivado 12-12493] Simulation top is 'pl_top_tb'
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.1/tps/boost_1_72_0'
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.1/data/xsim/xsim.ini' copied to run dir:'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'pl_top_tb' in fileset 'sim_1'...
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|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
|
|
INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mif'
|
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mif'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_0_mixed.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_1_wb.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_2_nm.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_4_mx.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_2_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/mode_1_memory_3_sp.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_axi_smc_0.mem'
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INFO: [SIM-utils-43] Exported 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim/sc_xtlm_design_a9_1_smartconnect_0_0.mem'
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xvlog --incr --relax -L uvm -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -prj pl_top_tb_vlog.prj"
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/sim/bd_962a.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bd_962a
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INFO: [VRFC 10-311] analyzing module clk_map_imp_MO2W24
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INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_1AX6TQV
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INFO: [VRFC 10-311] analyzing module m00_nodes_imp_1X4T3QZ
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INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_BPMQL0
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INFO: [VRFC 10-311] analyzing module s00_nodes_imp_HMS2Z2
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INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_1D6QMRK
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INFO: [VRFC 10-311] analyzing module s01_nodes_imp_193AQ2G
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INFO: [VRFC 10-311] analyzing module switchboards_imp_NFUYHM
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/sim/design_a9_1_smartconnect_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_smartconnect_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/sim/design_a9_1_xlconcat_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_xlconcat_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.ip_user_files/bd/design_a9_1/sim/design_a9_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/accel/accel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module accel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_arrange
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_spi
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module breath_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_a9_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_emg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_upload
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pwm_gen
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/run_time.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module run_time
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_intan
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_protocol_ql
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_sort
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/upload/upload_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module upload_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/c64pro_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module c64pro_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_mon_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_ch_map
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cur_monitor
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module acq_collect
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_if
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ad7689_dual_ctrl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/stim_config.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module stim_config
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top1
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ads1299_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_mod
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module pl_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module eeg_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module spi_full_duplex_master_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb_stim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb_stim
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module rhs2116_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module sine_gen_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/led_ctrl_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module led_ctrl_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/trigger/trigger_top_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trigger_top_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/channel_switch_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module channel_switch_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/switch/adg1414_if_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adg1414_if_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module transmit_config_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module cnv_res_collect_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer_tb.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module trans_timer_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_stub.v:18]
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.v:18]
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_cdc_sync_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_axis
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_base
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_reg_bit
|
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_fifo_rst
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32_xpm_memory_base
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axis_data_fifo_w32_d32
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WARNING: [VRFC 10-3609] overwriting previous definition of module 'axis_data_fifo_w32_d32' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/synth/axis_data_fifo_w32_d32.v:58]
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"xvhdl --incr --relax -prj pl_top_tb_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/axis_data_fifo_w32_d32_sim_netlist.vhdl" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_cdc_sync_rst'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized0_0\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1\'
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INFO: [VRFC 10-3107] analyzing entity '\axis_data_fifo_w32_d32_xpm_counter_updn__parameterized1_1\'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_reg_bit'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_rst'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_memory_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_base'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_xpm_fifo_axis'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32_axis_data_fifo_v2_0_10_top'
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INFO: [VRFC 10-3107] analyzing entity 'axis_data_fifo_w32_d32'
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run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 4086.809 ; gain = 0.000
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INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log"
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Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:511]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:519]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:624]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:628]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:638]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:676]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:680]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:690]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
|
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
|
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
|
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
|
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
|
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
|
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run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:26 . Memory (MB): peak = 4086.809 ; gain = 0.000
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INFO: [USF-XSim-69] 'elaborate' step finished in '26' seconds
|
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INFO: [USF-XSim-4] XSim::Simulate design
|
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/sim_1/behav/xsim'
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INFO: [USF-XSim-98] *** Running xsim
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with args "pl_top_tb_behav -key {Behavioral:sim_1:Functional:pl_top_tb} -tclbatch {pl_top_tb.tcl} -protoinst "protoinst_files/bd_6e35.protoinst" -protoinst "protoinst_files/bd_962a.protoinst" -protoinst "protoinst_files/design_a9_1.protoinst" -view {D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
|
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_6e35.protoinst
|
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_6e35.protoinst for the following reason(s):
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There are no instances of module "bd_6e35" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_962a.protoinst
|
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_962a.protoinst for the following reason(s):
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There are no instances of module "bd_962a" in the design.
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INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_a9_1.protoinst
|
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WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_a9_1.protoinst for the following reason(s):
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There are no instances of module "design_a9_1" in the design.
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Time resolution is 1 ps
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open_wave_config D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.sim/pl_top_tb_behav.wcfg
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source pl_top_tb.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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xsim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 4086.809 ; gain = 0.000
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'pl_top_tb_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:47 ; elapsed = 00:01:18 . Memory (MB): peak = 4086.809 ; gain = 0.000
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restart
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INFO: [Wavedata 42-604] Simulation restarted
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run 10 ms
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WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/u_axis_stream_data_fifo_rs/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_16 Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u0_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
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Time: 1 ps Iteration: 0 Process: /pl_top_tb/DUT/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial304_4236 Scope: pl_top_tb.DUT.u1_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
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run: Time (s): cpu = 00:01:22 ; elapsed = 00:02:13 . Memory (MB): peak = 4201.461 ; gain = 114.652
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tlast -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 16:58:09
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 16:58:09
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 16:59:32
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 16:59:32
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/m_axis_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 17:00:39
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 17:00:39
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/m_axis_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 17:01:35
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 17:01:35
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property CONTROL.TRIGGER_POSITION 500 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tlast -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 17:02:49
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 17:02:49
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes u_pl_top/u_eeg_emg_upload/eeg_emg_tlast -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 17:03:21
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 17:03:21
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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set_property CONTROL.TRIGGER_POSITION 200 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2026-Sep-02 17:03:41
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wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]
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display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"u_ila_0"}]]
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INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2026-Sep-02 17:03:41
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INFO: [Labtools 27-3304] ILA Waveform data saved to file D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
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display_hw_ila_data: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4211.465 ; gain = 0.000
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210251584078
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close_hw_manager
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current_wave_config {pl_top_tb_behav.wcfg}
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WARNING: [Wavedata 42-16] Error Unable to get wave configuration 'pl_top_tb_behav.wcfg'.
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add_wave {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /clk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /rst_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /upload_enable}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /upload_round}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /t_cs_n}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /t_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /t_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /t_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /t_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /cnv_res_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /cnv_res_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /cnv_res_tready}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /cnv_res_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /cs}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /sclk}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /mosi}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /miso}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tdata_w}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tlast_w}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_tvalid_w}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /res_tdata}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /res_tlast}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /res_tvalid}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /slv_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /r_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /byte_cnt}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /word}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /res_tvalid_b}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /res_tlast_b}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /ch}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /SPI_CLK_DIV}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /SPI_DATA_WIDTH}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /SPI_SLAVE_QTY}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /SPI_CNV_BYTES}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /IDLE}} {{/pl_top_tb/DUT/u1_eeg_top/\trans_if[0].u_ads1299_if /UPLOAD_ST}}
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