1753 lines
238 KiB
Plaintext
1753 lines
238 KiB
Plaintext
#-----------------------------------------------------------
|
|
# Vivado v2023.1 (64-bit)
|
|
# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
|
|
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
|
|
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
|
|
# Start of session at: Thu Aug 20 09:55:07 2026
|
|
# Process ID: 14448
|
|
# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v3
|
|
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16236 D:\Project\spinal_stim\pl\spinal_stim_v3\c64_pro.xpr
|
|
# Log file: D:/Project/spinal_stim/pl/spinal_stim_v3/vivado.log
|
|
# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v3\vivado.jou
|
|
# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
|
|
#-----------------------------------------------------------
|
|
start_gui
|
|
open_project D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.xpr
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.3 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.3/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.1 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
|
|
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
|
|
INFO: [Project 1-313] Project file moved from 'D:/Project/spinal_stim/pl/spinal_stim_v2' since last save.
|
|
Scanning sources...
|
|
Finished scanning sources
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
|
|
open_project: Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 2700.004 ; gain = 544.289
|
|
open_bd_design {D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd}
|
|
Reading block design file <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd>...
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_2
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_3
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_4
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_1
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_0
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_1
|
|
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
|
|
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_50M
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
|
|
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - CHANN_EN
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - CHANN_SEL
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - RST_AD5941
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - ZCHECK_SPI
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - Z_IO
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_5
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - ELEC_MUX_IN
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_2
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_2
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_3
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_3
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - STIM_SPI
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - GPIO
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_6
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_7
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - CUR_SPI
|
|
Successfully read diagram <design_a9_1> from block design file <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd>
|
|
open_bd_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:16 . Memory (MB): peak = 2885.121 ; gain = 25.371
|
|
WARNING: [IP_Flow 19-474] Invalid Parameter 'Component_Name'
|
|
startgroup
|
|
set_property -dict [list \
|
|
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {700} \
|
|
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
|
|
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
|
|
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
|
|
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
|
|
] [get_bd_cells processing_system7_0]
|
|
endgroup
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_smartconnect_0_0: SmartConnect design_a9_1_smartconnect_0_0 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2963.602 ; gain = 4.449
|
|
INFO: [BD 5-943] Reserving offset range <0x4000_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4120_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4200_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M02_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4400_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M03_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4126_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M04_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4600_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M05_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4041_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M06_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4040_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M07_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4042_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M08_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4800_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M09_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4121_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M10_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4122_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M11_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4123_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M12_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4043_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M13_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E0_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M14_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E2_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M15_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4124_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M16_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4A00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M17_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4C00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M18_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4125_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M19_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4E00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M20_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E1_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M21_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_axi_smc_0: SmartConnect design_a9_1_axi_smc_0 is in Low-Area Mode.
|
|
WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_axi_smc_0: IP design_a9_1_axi_smc_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S00_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 3113.434 ; gain = 119.719
|
|
xit::source_ipfile: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 3134.211 ; gain = 20.777
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /CUR_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /STIM_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /ZCHECK_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
validate_bd_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 3134.211 ; gain = 175.059
|
|
save_bd_design
|
|
Wrote : <D:\Project\spinal_stim\pl\spinal_stim_v3\c64_pro.srcs\sources_1\bd\design_a9_1\design_a9_1.bd>
|
|
Wrote : <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/ui/bd_41f4054b.ui>
|
|
save_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 3135.668 ; gain = 1.457
|
|
close_bd_design [get_bd_designs design_a9_1]
|
|
reset_run synth_1
|
|
reset_run design_a9_1_processing_system7_0_0_synth_1
|
|
launch_runs synth_1 -jobs 20
|
|
INFO: [BD 41-1662] The design 'design_a9_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/sim/design_a9_1.v
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_awid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_awid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_rid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_rid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_bid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_bid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_arid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_arid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AR_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AW_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_w_node/s_sc_payld'(65) to pin: '/s00_nodes/S_SC_W_payld'(63) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(157) to pin: '/m00_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(157) to pin: '/m00_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_w_payld'(63) to pin: '/m00_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(157) to pin: '/m01_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(157) to pin: '/m01_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_w_payld'(63) to pin: '/m01_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(157) to pin: '/m02_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(157) to pin: '/m02_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_w_payld'(63) to pin: '/m02_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(157) to pin: '/m03_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(157) to pin: '/m03_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_w_payld'(63) to pin: '/m03_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(157) to pin: '/m04_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(157) to pin: '/m04_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_w_payld'(63) to pin: '/m04_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_ar_payld'(157) to pin: '/m05_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_aw_payld'(157) to pin: '/m05_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_w_payld'(63) to pin: '/m05_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_ar_payld'(157) to pin: '/m06_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_aw_payld'(157) to pin: '/m06_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_w_payld'(63) to pin: '/m06_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_ar_payld'(157) to pin: '/m07_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_aw_payld'(157) to pin: '/m07_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_w_payld'(63) to pin: '/m07_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_ar_payld'(157) to pin: '/m08_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_aw_payld'(157) to pin: '/m08_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_w_payld'(63) to pin: '/m08_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_ar_payld'(157) to pin: '/m09_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_aw_payld'(157) to pin: '/m09_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_w_payld'(63) to pin: '/m09_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_ar_payld'(157) to pin: '/m10_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_aw_payld'(157) to pin: '/m10_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_w_payld'(63) to pin: '/m10_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_ar_payld'(157) to pin: '/m11_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_aw_payld'(157) to pin: '/m11_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_w_payld'(63) to pin: '/m11_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_ar_payld'(157) to pin: '/m12_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_aw_payld'(157) to pin: '/m12_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_w_payld'(63) to pin: '/m12_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_ar_payld'(157) to pin: '/m13_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_aw_payld'(157) to pin: '/m13_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_w_payld'(63) to pin: '/m13_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_ar_payld'(157) to pin: '/m14_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_aw_payld'(157) to pin: '/m14_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_w_payld'(63) to pin: '/m14_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_ar_payld'(157) to pin: '/m15_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_aw_payld'(157) to pin: '/m15_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_w_payld'(63) to pin: '/m15_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_ar_payld'(157) to pin: '/m16_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_aw_payld'(157) to pin: '/m16_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_w_payld'(63) to pin: '/m16_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_ar_payld'(157) to pin: '/m17_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_aw_payld'(157) to pin: '/m17_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_w_payld'(63) to pin: '/m17_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_ar_payld'(157) to pin: '/m18_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_aw_payld'(157) to pin: '/m18_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_w_payld'(63) to pin: '/m18_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_ar_payld'(157) to pin: '/m19_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_aw_payld'(157) to pin: '/m19_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_w_payld'(63) to pin: '/m19_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_ar_payld'(157) to pin: '/m20_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_aw_payld'(157) to pin: '/m20_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_w_payld'(63) to pin: '/m20_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_ar_payld'(157) to pin: '/m21_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_aw_payld'(157) to pin: '/m21_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_w_payld'(63) to pin: '/m21_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_awid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_awid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_rid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_rid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_bid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_bid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_arid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_arid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AR_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AW_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_w_node/s_sc_payld'(65) to pin: '/s00_nodes/S_SC_W_payld'(63) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(157) to pin: '/m00_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(157) to pin: '/m00_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_w_payld'(63) to pin: '/m00_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(157) to pin: '/m01_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(157) to pin: '/m01_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_w_payld'(63) to pin: '/m01_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(157) to pin: '/m02_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(157) to pin: '/m02_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_w_payld'(63) to pin: '/m02_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(157) to pin: '/m03_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(157) to pin: '/m03_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_w_payld'(63) to pin: '/m03_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(157) to pin: '/m04_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(157) to pin: '/m04_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_w_payld'(63) to pin: '/m04_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_ar_payld'(157) to pin: '/m05_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_aw_payld'(157) to pin: '/m05_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_w_payld'(63) to pin: '/m05_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_ar_payld'(157) to pin: '/m06_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_aw_payld'(157) to pin: '/m06_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
INFO: [Common 17-14] Message 'BD 41-2384' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/hw_handoff/design_a9_1_axi_smc_0.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/synth/design_a9_1_axi_smc_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
|
|
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
|
|
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0'. A default connection has been created.
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/hw_handoff/design_a9_1_smartconnect_0_0.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/synth/design_a9_1_smartconnect_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/hw_handoff/design_a9_1.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.hwdef
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_a9_1_axi_smc_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_a9_1_smartconnect_0_0
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_a9_1_axi_smc_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_a9_1_smartconnect_0_0
|
|
[Thu Aug 20 10:13:38 2026] Launched design_a9_1_processing_system7_0_0_synth_1, design_a9_1_smartconnect_0_0_synth_1, design_a9_1_axi_smc_0_synth_1...
|
|
Run output will be captured here:
|
|
design_a9_1_processing_system7_0_0_synth_1: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/design_a9_1_processing_system7_0_0_synth_1/runme.log
|
|
design_a9_1_smartconnect_0_0_synth_1: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/design_a9_1_smartconnect_0_0_synth_1/runme.log
|
|
design_a9_1_axi_smc_0_synth_1: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/design_a9_1_axi_smc_0_synth_1/runme.log
|
|
[Thu Aug 20 10:13:39 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/synth_1/runme.log
|
|
launch_runs: Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3653.723 ; gain = 456.098
|
|
open_run synth_1 -name synth_1
|
|
Design is defaulting to impl run constrset: constrs_1
|
|
Design is defaulting to synth run part: xc7z020clg400-2
|
|
INFO: [Device 21-403] Loading part xc7z020clg400-2
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.dcp' for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp' for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32.dcp' for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.dcp' for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
|
|
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4104.180 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.1
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Chipscope 16-324] Core: u_pl_top/u_cur_mon_top/u_vio_cur_flt_state UUID: 8a67dbc2-bda6-5e4b-b982-bb6511a2b4be
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc:50]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
INFO: [Project 1-1714] 477 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 4848.281 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 188 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 27 instances
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 3 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 144 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 14 instances
|
|
|
|
open_run: Time (s): cpu = 00:00:54 ; elapsed = 00:00:41 . Memory (MB): peak = 4878.039 ; gain = 773.859
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/m_axis_record_tkeep[0]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/axi_i_out[0]} {u_pl_top/axi_i_out[1]} {u_pl_top/axi_i_out[2]} {u_pl_top/axi_i_out[3]} {u_pl_top/axi_i_out[4]} {u_pl_top/axi_i_out[5]} {u_pl_top/axi_i_out[6]} {u_pl_top/axi_i_out[7]} {u_pl_top/axi_i_out[8]} {u_pl_top/axi_i_out[9]} {u_pl_top/axi_i_out[10]} {u_pl_top/axi_i_out[11]} {u_pl_top/axi_i_out[12]} {u_pl_top/axi_i_out[13]} {u_pl_top/axi_i_out[14]} {u_pl_top/axi_i_out[15]} {u_pl_top/axi_i_out[16]} {u_pl_top/axi_i_out[17]} {u_pl_top/axi_i_out[18]} {u_pl_top/axi_i_out[19]} {u_pl_top/axi_i_out[20]} {u_pl_top/axi_i_out[21]} {u_pl_top/axi_i_out[22]} {u_pl_top/axi_i_out[23]} {u_pl_top/axi_i_out[24]} {u_pl_top/axi_i_out[25]} {u_pl_top/axi_i_out[26]} {u_pl_top/axi_i_out[27]} {u_pl_top/axi_i_out[28]} {u_pl_top/axi_i_out[29]} {u_pl_top/axi_i_out[30]} {u_pl_top/axi_i_out[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axi_i_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/axi_i_wr ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list mux_pwr_en_OBUF ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs synth_1 -jobs 20
|
|
[Thu Aug 20 10:26:41 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/synth_1/runme.log
|
|
launch_runs impl_1 -jobs 20
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
|
|
[Thu Aug 20 10:30:40 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/impl_1/runme.log
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
[Thu Aug 20 10:44:53 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/impl_1/runme.log
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa
|
|
INFO: [Project 1-1918] Creating Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa ...
|
|
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
|
|
INFO: [Project 1-1941] Successfully created Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa
|
|
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2023.1/data/embeddedsw) loading 0 seconds
|
|
open_bd_design {D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd}
|
|
Reading block design file <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd>...
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_2
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_3
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_4
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_1
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_0
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_1
|
|
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
|
|
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_50M
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
|
|
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - CHANN_EN
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - CHANN_SEL
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - RST_AD5941
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - ZCHECK_SPI
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - Z_IO
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_5
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - ELEC_MUX_IN
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_2
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_2
|
|
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_3
|
|
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_3
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - STIM_SPI
|
|
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - GPIO
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_6
|
|
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_7
|
|
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - CUR_SPI
|
|
Successfully read diagram <design_a9_1> from block design file <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/design_a9_1.bd>
|
|
open_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 5093.469 ; gain = 0.000
|
|
WARNING: [IP_Flow 19-474] Invalid Parameter 'Component_Name'
|
|
startgroup
|
|
set_property -dict [list \
|
|
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
|
|
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
|
|
CONFIG.PCW_ENET0_RESET_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
] [get_bd_cells processing_system7_0]
|
|
endgroup
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 512M ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_smartconnect_0_0: SmartConnect design_a9_1_smartconnect_0_0 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 5093.469 ; gain = 0.000
|
|
INFO: [BD 5-943] Reserving offset range <0x4000_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4120_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4200_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M02_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4400_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M03_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4126_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M04_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4600_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M05_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4041_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M06_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4040_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M07_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4042_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M08_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4800_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M09_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4121_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M10_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4122_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M11_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4123_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M12_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4043_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M13_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E0_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M14_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E2_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M15_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4124_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M16_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4A00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M17_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4C00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M18_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4125_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M19_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x4E00_0000 [ 8K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M20_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x41E1_0000 [ 64K ]> from slave interface '/axi_smc/S00_AXI' to master interface '/axi_smc/M21_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_axi_smc_0: SmartConnect design_a9_1_axi_smc_0 is in Low-Area Mode.
|
|
WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_a9_1_axi_smc_0: IP design_a9_1_axi_smc_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S00_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 5097.863 ; gain = 0.000
|
|
xit::source_ipfile: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 5097.945 ; gain = 0.082
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /ZCHECK_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /STIM_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /CUR_SPI
|
|
#######################################################################################
|
|
INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
|
|
########################################################################################
|
|
validate_bd_design: Time (s): cpu = 00:01:11 ; elapsed = 00:01:12 . Memory (MB): peak = 5097.945 ; gain = 4.477
|
|
save_bd_design
|
|
Wrote : <D:\Project\spinal_stim\pl\spinal_stim_v3\c64_pro.srcs\sources_1\bd\design_a9_1\design_a9_1.bd>
|
|
Wrote : <D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/sources_1/bd/design_a9_1/ui/bd_41f4054b.ui>
|
|
save_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 5097.945 ; gain = 0.000
|
|
close_bd_design [get_bd_designs design_a9_1]
|
|
reset_run synth_1
|
|
reset_run design_a9_1_processing_system7_0_0_synth_1
|
|
reset_run design_a9_1_smartconnect_0_0_synth_1
|
|
reset_run design_a9_1_axi_smc_0_synth_1
|
|
launch_runs synth_1 -jobs 20
|
|
INFO: [BD 41-1662] The design 'design_a9_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/sim/design_a9_1.v
|
|
Verilog Output written to : d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_awid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_awid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_rid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_rid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_bid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_bid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_arid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_arid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AR_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AW_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_w_node/s_sc_payld'(65) to pin: '/s00_nodes/S_SC_W_payld'(63) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(157) to pin: '/m00_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(157) to pin: '/m00_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_w_payld'(63) to pin: '/m00_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(157) to pin: '/m01_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(157) to pin: '/m01_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_w_payld'(63) to pin: '/m01_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(157) to pin: '/m02_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(157) to pin: '/m02_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_w_payld'(63) to pin: '/m02_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(157) to pin: '/m03_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(157) to pin: '/m03_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_w_payld'(63) to pin: '/m03_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(157) to pin: '/m04_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(157) to pin: '/m04_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_w_payld'(63) to pin: '/m04_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_ar_payld'(157) to pin: '/m05_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_aw_payld'(157) to pin: '/m05_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_w_payld'(63) to pin: '/m05_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_ar_payld'(157) to pin: '/m06_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_aw_payld'(157) to pin: '/m06_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_w_payld'(63) to pin: '/m06_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_ar_payld'(157) to pin: '/m07_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_aw_payld'(157) to pin: '/m07_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_w_payld'(63) to pin: '/m07_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_ar_payld'(157) to pin: '/m08_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_aw_payld'(157) to pin: '/m08_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_w_payld'(63) to pin: '/m08_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_ar_payld'(157) to pin: '/m09_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_aw_payld'(157) to pin: '/m09_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_w_payld'(63) to pin: '/m09_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_ar_payld'(157) to pin: '/m10_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_aw_payld'(157) to pin: '/m10_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_w_payld'(63) to pin: '/m10_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_ar_payld'(157) to pin: '/m11_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_aw_payld'(157) to pin: '/m11_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m11_sc2axi/s_sc_w_payld'(63) to pin: '/m11_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_ar_payld'(157) to pin: '/m12_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_aw_payld'(157) to pin: '/m12_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m12_sc2axi/s_sc_w_payld'(63) to pin: '/m12_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_ar_payld'(157) to pin: '/m13_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_aw_payld'(157) to pin: '/m13_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m13_sc2axi/s_sc_w_payld'(63) to pin: '/m13_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_ar_payld'(157) to pin: '/m14_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_aw_payld'(157) to pin: '/m14_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m14_sc2axi/s_sc_w_payld'(63) to pin: '/m14_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_ar_payld'(157) to pin: '/m15_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_aw_payld'(157) to pin: '/m15_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m15_sc2axi/s_sc_w_payld'(63) to pin: '/m15_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_ar_payld'(157) to pin: '/m16_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_aw_payld'(157) to pin: '/m16_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m16_sc2axi/s_sc_w_payld'(63) to pin: '/m16_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_ar_payld'(157) to pin: '/m17_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_aw_payld'(157) to pin: '/m17_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m17_sc2axi/s_sc_w_payld'(63) to pin: '/m17_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_ar_payld'(157) to pin: '/m18_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_aw_payld'(157) to pin: '/m18_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m18_sc2axi/s_sc_w_payld'(63) to pin: '/m18_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_ar_payld'(157) to pin: '/m19_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_aw_payld'(157) to pin: '/m19_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m19_sc2axi/s_sc_w_payld'(63) to pin: '/m19_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_ar_payld'(157) to pin: '/m20_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_aw_payld'(157) to pin: '/m20_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m20_sc2axi/s_sc_w_payld'(63) to pin: '/m20_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_ar_payld'(157) to pin: '/m21_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_aw_payld'(157) to pin: '/m21_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m21_sc2axi/s_sc_w_payld'(63) to pin: '/m21_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_awid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_awid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_rid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_rid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_bid'(3) to pin: '/s00_entry_pipeline/s00_si_converter/s_axi_bid'(5) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_entry_pipeline/s00_si_converter/s_axi_arid'(5) to pin: '/s00_entry_pipeline/s00_transaction_regulator/m_axi_arid'(3) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AR_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(159) to pin: '/s00_nodes/S_SC_AW_payld'(157) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_w_node/s_sc_payld'(65) to pin: '/s00_nodes/S_SC_W_payld'(63) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(157) to pin: '/m00_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(157) to pin: '/m00_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_w_payld'(63) to pin: '/m00_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(157) to pin: '/m01_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(157) to pin: '/m01_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_w_payld'(63) to pin: '/m01_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(157) to pin: '/m02_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(157) to pin: '/m02_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_w_payld'(63) to pin: '/m02_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(157) to pin: '/m03_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(157) to pin: '/m03_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_w_payld'(63) to pin: '/m03_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(157) to pin: '/m04_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(157) to pin: '/m04_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_w_payld'(63) to pin: '/m04_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_ar_payld'(157) to pin: '/m05_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_aw_payld'(157) to pin: '/m05_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_w_payld'(63) to pin: '/m05_nodes/M_SC_W_payld'(65) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_ar_payld'(157) to pin: '/m06_nodes/M_SC_AR_payld'(159) - Only lower order bits will be connected.
|
|
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_aw_payld'(157) to pin: '/m06_nodes/M_SC_AW_payld'(159) - Only lower order bits will be connected.
|
|
INFO: [Common 17-14] Message 'BD 41-2384' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/hw_handoff/design_a9_1_axi_smc_0.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/synth/design_a9_1_axi_smc_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
|
|
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
|
|
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0'. A default connection has been created.
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/hw_handoff/design_a9_1_smartconnect_0_0.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/synth/design_a9_1_smartconnect_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
Exporting to file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/hw_handoff/design_a9_1.hwh
|
|
Generated Hardware Definition File d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.hwdef
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_a9_1_axi_smc_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_a9_1_smartconnect_0_0
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_a9_1_axi_smc_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 406bd5ab20d6eba0 to dir: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/4/0/406bd5ab20d6eba0/design_a9_1_axi_smc_0.dcp to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/4/0/406bd5ab20d6eba0/design_a9_1_axi_smc_0_sim_netlist.v to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/4/0/406bd5ab20d6eba0/design_a9_1_axi_smc_0_sim_netlist.vhdl to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/4/0/406bd5ab20d6eba0/design_a9_1_axi_smc_0_stub.v to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/4/0/406bd5ab20d6eba0/design_a9_1_axi_smc_0_stub.vhdl to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_a9_1_axi_smc_0, cache-ID = 406bd5ab20d6eba0; cache size = 1431.329 MB.
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_a9_1_smartconnect_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 3c6bbcbcc9068e37 to dir: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0.dcp to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0_sim_netlist.v to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0_sim_netlist.vhdl to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0_stub.v to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.cache/ip/2023.1/3/c/3c6bbcbcc9068e37/design_a9_1_smartconnect_0_0_stub.vhdl to d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_a9_1_smartconnect_0_0, cache-ID = 3c6bbcbcc9068e37; cache size = 1431.329 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 5258.250 ; gain = 9.285
|
|
[Thu Aug 20 13:41:47 2026] Launched design_a9_1_processing_system7_0_0_synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/design_a9_1_processing_system7_0_0_synth_1/runme.log
|
|
[Thu Aug 20 13:41:47 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/synth_1/runme.log
|
|
launch_runs: Time (s): cpu = 00:01:44 ; elapsed = 00:01:39 . Memory (MB): peak = 5258.250 ; gain = 160.305
|
|
close_design
|
|
open_run synth_1 -name synth_1
|
|
Design is defaulting to impl run constrset: constrs_1
|
|
Design is defaulting to synth run part: xc7z020clg400-2
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128.dcp' for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.dcp' for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.dcp' for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32.dcp' for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.dcp' for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
|
|
INFO: [Project 1-454] Reading design checkpoint 'd:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0.dcp' for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
|
|
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5258.250 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.1
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Chipscope 16-324] Core: u_pl_top/u_cur_mon_top/u_vio_cur_flt_state UUID: 8a67dbc2-bda6-5e4b-b982-bb6511a2b4be
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/bd_0/ip/ip_1/bd_6e35_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0/inst'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/bd_0/ip/ip_1/bd_962a_psr_aclk_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:52]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:56]
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc:61]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_board.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
|
|
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc:50]
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_clocks.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v3/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1_clocks.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0'
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/CUR_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/STIM_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_ps_a9_1/design_a9_1_i/ZCHECK_SPI/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
|
|
Instance: u_pl_top/u_cur_mon_top/u0_fifo_generator_1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst
|
|
This will add unnecessary latency to the design. Please check the design for the following:
|
|
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
|
|
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
|
|
[C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
|
|
INFO: [Project 1-1714] 477 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.041 . Memory (MB): peak = 5339.742 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 188 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 27 instances
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 3 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 144 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 14 instances
|
|
|
|
open_run: Time (s): cpu = 00:00:50 ; elapsed = 00:00:38 . Memory (MB): peak = 5339.742 ; gain = 81.492
|
|
create_debug_core u_ila_0 ila
|
|
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
connect_debug_port u_ila_0/clk [get_nets [list u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 ]]
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
connect_debug_port u_ila_0/probe0 [get_nets [list {u_pl_top/axis_emg_tdata[0]} {u_pl_top/axis_emg_tdata[1]} {u_pl_top/axis_emg_tdata[2]} {u_pl_top/axis_emg_tdata[3]} {u_pl_top/axis_emg_tdata[4]} {u_pl_top/axis_emg_tdata[5]} {u_pl_top/axis_emg_tdata[6]} {u_pl_top/axis_emg_tdata[7]} {u_pl_top/axis_emg_tdata[8]} {u_pl_top/axis_emg_tdata[9]} {u_pl_top/axis_emg_tdata[10]} {u_pl_top/axis_emg_tdata[11]} {u_pl_top/axis_emg_tdata[12]} {u_pl_top/axis_emg_tdata[13]} {u_pl_top/axis_emg_tdata[14]} {u_pl_top/axis_emg_tdata[15]} {u_pl_top/axis_emg_tdata[16]} {u_pl_top/axis_emg_tdata[17]} {u_pl_top/axis_emg_tdata[18]} {u_pl_top/axis_emg_tdata[19]} {u_pl_top/axis_emg_tdata[20]} {u_pl_top/axis_emg_tdata[21]} {u_pl_top/axis_emg_tdata[22]} {u_pl_top/axis_emg_tdata[23]} {u_pl_top/axis_emg_tdata[24]} {u_pl_top/axis_emg_tdata[25]} {u_pl_top/axis_emg_tdata[26]} {u_pl_top/axis_emg_tdata[27]} {u_pl_top/axis_emg_tdata[28]} {u_pl_top/axis_emg_tdata[29]} {u_pl_top/axis_emg_tdata[30]} {u_pl_top/axis_emg_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
connect_debug_port u_ila_0/probe1 [get_nets [list {u_pl_top/axis_emg_tdata_tmp[0]} {u_pl_top/axis_emg_tdata_tmp[1]} {u_pl_top/axis_emg_tdata_tmp[2]} {u_pl_top/axis_emg_tdata_tmp[3]} {u_pl_top/axis_emg_tdata_tmp[4]} {u_pl_top/axis_emg_tdata_tmp[5]} {u_pl_top/axis_emg_tdata_tmp[6]} {u_pl_top/axis_emg_tdata_tmp[7]} {u_pl_top/axis_emg_tdata_tmp[8]} {u_pl_top/axis_emg_tdata_tmp[9]} {u_pl_top/axis_emg_tdata_tmp[10]} {u_pl_top/axis_emg_tdata_tmp[11]} {u_pl_top/axis_emg_tdata_tmp[12]} {u_pl_top/axis_emg_tdata_tmp[13]} {u_pl_top/axis_emg_tdata_tmp[14]} {u_pl_top/axis_emg_tdata_tmp[15]} {u_pl_top/axis_emg_tdata_tmp[16]} {u_pl_top/axis_emg_tdata_tmp[17]} {u_pl_top/axis_emg_tdata_tmp[18]} {u_pl_top/axis_emg_tdata_tmp[19]} {u_pl_top/axis_emg_tdata_tmp[20]} {u_pl_top/axis_emg_tdata_tmp[21]} {u_pl_top/axis_emg_tdata_tmp[22]} {u_pl_top/axis_emg_tdata_tmp[23]} {u_pl_top/axis_emg_tdata_tmp[24]} {u_pl_top/axis_emg_tdata_tmp[25]} {u_pl_top/axis_emg_tdata_tmp[26]} {u_pl_top/axis_emg_tdata_tmp[27]} {u_pl_top/axis_emg_tdata_tmp[28]} {u_pl_top/axis_emg_tdata_tmp[29]} {u_pl_top/axis_emg_tdata_tmp[30]} {u_pl_top/axis_emg_tdata_tmp[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
connect_debug_port u_ila_0/probe2 [get_nets [list {u_pl_top/axis_eeg24_tdata[0]} {u_pl_top/axis_eeg24_tdata[1]} {u_pl_top/axis_eeg24_tdata[2]} {u_pl_top/axis_eeg24_tdata[3]} {u_pl_top/axis_eeg24_tdata[4]} {u_pl_top/axis_eeg24_tdata[5]} {u_pl_top/axis_eeg24_tdata[6]} {u_pl_top/axis_eeg24_tdata[7]} {u_pl_top/axis_eeg24_tdata[8]} {u_pl_top/axis_eeg24_tdata[9]} {u_pl_top/axis_eeg24_tdata[10]} {u_pl_top/axis_eeg24_tdata[11]} {u_pl_top/axis_eeg24_tdata[12]} {u_pl_top/axis_eeg24_tdata[13]} {u_pl_top/axis_eeg24_tdata[14]} {u_pl_top/axis_eeg24_tdata[15]} {u_pl_top/axis_eeg24_tdata[16]} {u_pl_top/axis_eeg24_tdata[17]} {u_pl_top/axis_eeg24_tdata[18]} {u_pl_top/axis_eeg24_tdata[19]} {u_pl_top/axis_eeg24_tdata[20]} {u_pl_top/axis_eeg24_tdata[21]} {u_pl_top/axis_eeg24_tdata[22]} {u_pl_top/axis_eeg24_tdata[23]} {u_pl_top/axis_eeg24_tdata[24]} {u_pl_top/axis_eeg24_tdata[25]} {u_pl_top/axis_eeg24_tdata[26]} {u_pl_top/axis_eeg24_tdata[27]} {u_pl_top/axis_eeg24_tdata[28]} {u_pl_top/axis_eeg24_tdata[29]} {u_pl_top/axis_eeg24_tdata[30]} {u_pl_top/axis_eeg24_tdata[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe3]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
connect_debug_port u_ila_0/probe3 [get_nets [list {u_pl_top/emg_send_package_num[0]} {u_pl_top/emg_send_package_num[1]} {u_pl_top/emg_send_package_num[2]} {u_pl_top/emg_send_package_num[3]} {u_pl_top/emg_send_package_num[4]} {u_pl_top/emg_send_package_num[5]} {u_pl_top/emg_send_package_num[6]} {u_pl_top/emg_send_package_num[7]} {u_pl_top/emg_send_package_num[8]} {u_pl_top/emg_send_package_num[9]} {u_pl_top/emg_send_package_num[10]} {u_pl_top/emg_send_package_num[11]} {u_pl_top/emg_send_package_num[12]} {u_pl_top/emg_send_package_num[13]} {u_pl_top/emg_send_package_num[14]} {u_pl_top/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
connect_debug_port u_ila_0/probe4 [get_nets [list {u_pl_top/m_axis_eeg_tdata[0]} {u_pl_top/m_axis_eeg_tdata[1]} {u_pl_top/m_axis_eeg_tdata[2]} {u_pl_top/m_axis_eeg_tdata[3]} {u_pl_top/m_axis_eeg_tdata[4]} {u_pl_top/m_axis_eeg_tdata[5]} {u_pl_top/m_axis_eeg_tdata[6]} {u_pl_top/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
connect_debug_port u_ila_0/probe5 [get_nets [list {u_pl_top/m_axis_emg_tdata[0]} {u_pl_top/m_axis_emg_tdata[1]} {u_pl_top/m_axis_emg_tdata[2]} {u_pl_top/m_axis_emg_tdata[3]} {u_pl_top/m_axis_emg_tdata[4]} {u_pl_top/m_axis_emg_tdata[5]} {u_pl_top/m_axis_emg_tdata[6]} {u_pl_top/m_axis_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe6]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
connect_debug_port u_ila_0/probe6 [get_nets [list {u_pl_top/eeg_emg_sel[0]} {u_pl_top/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe7]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
|
connect_debug_port u_ila_0/probe7 [get_nets [list {u_pl_top/eeg_send_package_num[0]} {u_pl_top/eeg_send_package_num[1]} {u_pl_top/eeg_send_package_num[2]} {u_pl_top/eeg_send_package_num[3]} {u_pl_top/eeg_send_package_num[4]} {u_pl_top/eeg_send_package_num[5]} {u_pl_top/eeg_send_package_num[6]} {u_pl_top/eeg_send_package_num[7]} {u_pl_top/eeg_send_package_num[8]} {u_pl_top/eeg_send_package_num[9]} {u_pl_top/eeg_send_package_num[10]} {u_pl_top/eeg_send_package_num[11]} {u_pl_top/eeg_send_package_num[12]} {u_pl_top/eeg_send_package_num[13]} {u_pl_top/eeg_send_package_num[14]} {u_pl_top/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe8]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
|
connect_debug_port u_ila_0/probe8 [get_nets [list {u_pl_top/m_axis_record_tdata[0]} {u_pl_top/m_axis_record_tdata[1]} {u_pl_top/m_axis_record_tdata[2]} {u_pl_top/m_axis_record_tdata[3]} {u_pl_top/m_axis_record_tdata[4]} {u_pl_top/m_axis_record_tdata[5]} {u_pl_top/m_axis_record_tdata[6]} {u_pl_top/m_axis_record_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
|
connect_debug_port u_ila_0/probe9 [get_nets [list {u_pl_top/axi_i_out[0]} {u_pl_top/axi_i_out[1]} {u_pl_top/axi_i_out[2]} {u_pl_top/axi_i_out[3]} {u_pl_top/axi_i_out[4]} {u_pl_top/axi_i_out[5]} {u_pl_top/axi_i_out[6]} {u_pl_top/axi_i_out[7]} {u_pl_top/axi_i_out[8]} {u_pl_top/axi_i_out[9]} {u_pl_top/axi_i_out[10]} {u_pl_top/axi_i_out[11]} {u_pl_top/axi_i_out[12]} {u_pl_top/axi_i_out[13]} {u_pl_top/axi_i_out[14]} {u_pl_top/axi_i_out[15]} {u_pl_top/axi_i_out[16]} {u_pl_top/axi_i_out[17]} {u_pl_top/axi_i_out[18]} {u_pl_top/axi_i_out[19]} {u_pl_top/axi_i_out[20]} {u_pl_top/axi_i_out[21]} {u_pl_top/axi_i_out[22]} {u_pl_top/axi_i_out[23]} {u_pl_top/axi_i_out[24]} {u_pl_top/axi_i_out[25]} {u_pl_top/axi_i_out[26]} {u_pl_top/axi_i_out[27]} {u_pl_top/axi_i_out[28]} {u_pl_top/axi_i_out[29]} {u_pl_top/axi_i_out[30]} {u_pl_top/axi_i_out[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
|
connect_debug_port u_ila_0/probe10 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16_out[0]} {u_pl_top/u_eeg_emg_upload/crc16_out[1]} {u_pl_top/u_eeg_emg_upload/crc16_out[2]} {u_pl_top/u_eeg_emg_upload/crc16_out[3]} {u_pl_top/u_eeg_emg_upload/crc16_out[4]} {u_pl_top/u_eeg_emg_upload/crc16_out[5]} {u_pl_top/u_eeg_emg_upload/crc16_out[6]} {u_pl_top/u_eeg_emg_upload/crc16_out[7]} {u_pl_top/u_eeg_emg_upload/crc16_out[8]} {u_pl_top/u_eeg_emg_upload/crc16_out[9]} {u_pl_top/u_eeg_emg_upload/crc16_out[10]} {u_pl_top/u_eeg_emg_upload/crc16_out[11]} {u_pl_top/u_eeg_emg_upload/crc16_out[12]} {u_pl_top/u_eeg_emg_upload/crc16_out[13]} {u_pl_top/u_eeg_emg_upload/crc16_out[14]} {u_pl_top/u_eeg_emg_upload/crc16_out[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 2 [get_debug_ports u_ila_0/probe11]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
|
connect_debug_port u_ila_0/probe11 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_sel[1]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
|
connect_debug_port u_ila_0/probe12 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
|
connect_debug_port u_ila_0/probe13 [get_nets [list {u_pl_top/u_eeg_emg_upload/crc16[0]} {u_pl_top/u_eeg_emg_upload/crc16[1]} {u_pl_top/u_eeg_emg_upload/crc16[2]} {u_pl_top/u_eeg_emg_upload/crc16[3]} {u_pl_top/u_eeg_emg_upload/crc16[4]} {u_pl_top/u_eeg_emg_upload/crc16[5]} {u_pl_top/u_eeg_emg_upload/crc16[6]} {u_pl_top/u_eeg_emg_upload/crc16[7]} {u_pl_top/u_eeg_emg_upload/crc16[8]} {u_pl_top/u_eeg_emg_upload/crc16[9]} {u_pl_top/u_eeg_emg_upload/crc16[10]} {u_pl_top/u_eeg_emg_upload/crc16[11]} {u_pl_top/u_eeg_emg_upload/crc16[12]} {u_pl_top/u_eeg_emg_upload/crc16[13]} {u_pl_top/u_eeg_emg_upload/crc16[14]} {u_pl_top/u_eeg_emg_upload/crc16[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
|
connect_debug_port u_ila_0/probe14 [get_nets [list {u_pl_top/u_eeg_emg_upload/emg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/emg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
|
connect_debug_port u_ila_0/probe15 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[8]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[9]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[10]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[11]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[12]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[13]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[14]} {u_pl_top/u_eeg_emg_upload/fifo_rd_en_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe16]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
|
connect_debug_port u_ila_0/probe16 [get_nets [list {u_pl_top/u_eeg_emg_upload/fifo_rd_data[0]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[1]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[2]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[3]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[4]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[5]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[6]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[7]} {u_pl_top/u_eeg_emg_upload/fifo_rd_data[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe17]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
|
connect_debug_port u_ila_0/probe17 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[0]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[1]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[2]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[3]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[4]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[5]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[6]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[7]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[8]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[9]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[10]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[11]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[12]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[13]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[14]} {u_pl_top/u_eeg_emg_upload/eeg_send_package_num[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
|
connect_debug_port u_ila_0/probe18 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[0]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[1]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[2]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[3]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[4]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[5]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[6]} {u_pl_top/u_eeg_emg_upload/eeg_emg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
|
connect_debug_port u_ila_0/probe19 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
|
connect_debug_port u_ila_0/probe20 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[0]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[1]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[2]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[3]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[4]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[5]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[6]} {u_pl_top/u_eeg_emg_upload/axis_eeg_tdata_tmp[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 9 [get_debug_ports u_ila_0/probe21]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
|
connect_debug_port u_ila_0/probe21 [get_nets [list {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[0]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[1]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[2]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[3]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[4]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[5]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[6]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[7]} {u_pl_top/u_eeg_emg_upload/axis_emg_fifo_tdata[8]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 16 [get_debug_ports u_ila_0/probe22]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
|
connect_debug_port u_ila_0/probe22 [get_nets [list {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[0]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[1]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[2]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[3]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[4]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[5]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[6]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[7]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[8]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[9]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[10]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[11]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[12]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[13]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[14]} {u_pl_top/u_eeg_emg_upload/eeg_data_cnt[15]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
|
connect_debug_port u_ila_0/probe23 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[1][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[1][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe24]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
|
connect_debug_port u_ila_0/probe24 [get_nets [list {u_pl_top/u_eeg_emg_upload/msg_crc[0][0]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][1]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][2]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][3]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][4]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][5]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][6]} {u_pl_top/u_eeg_emg_upload/msg_crc[0][7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 8 [get_debug_ports u_ila_0/probe25]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
|
connect_debug_port u_ila_0/probe25 [get_nets [list {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[0]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[1]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[2]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[3]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[4]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[5]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[6]} {u_pl_top/u_eeg_emg_upload/m_axis_eeg_tdata[7]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 32 [get_debug_ports u_ila_0/probe26]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
|
connect_debug_port u_ila_0/probe26 [get_nets [list {u_pl_top/u_stim_config/bram_din[0]} {u_pl_top/u_stim_config/bram_din[1]} {u_pl_top/u_stim_config/bram_din[2]} {u_pl_top/u_stim_config/bram_din[3]} {u_pl_top/u_stim_config/bram_din[4]} {u_pl_top/u_stim_config/bram_din[5]} {u_pl_top/u_stim_config/bram_din[6]} {u_pl_top/u_stim_config/bram_din[7]} {u_pl_top/u_stim_config/bram_din[8]} {u_pl_top/u_stim_config/bram_din[9]} {u_pl_top/u_stim_config/bram_din[10]} {u_pl_top/u_stim_config/bram_din[11]} {u_pl_top/u_stim_config/bram_din[12]} {u_pl_top/u_stim_config/bram_din[13]} {u_pl_top/u_stim_config/bram_din[14]} {u_pl_top/u_stim_config/bram_din[15]} {u_pl_top/u_stim_config/bram_din[16]} {u_pl_top/u_stim_config/bram_din[17]} {u_pl_top/u_stim_config/bram_din[18]} {u_pl_top/u_stim_config/bram_din[19]} {u_pl_top/u_stim_config/bram_din[20]} {u_pl_top/u_stim_config/bram_din[21]} {u_pl_top/u_stim_config/bram_din[22]} {u_pl_top/u_stim_config/bram_din[23]} {u_pl_top/u_stim_config/bram_din[24]} {u_pl_top/u_stim_config/bram_din[25]} {u_pl_top/u_stim_config/bram_din[26]} {u_pl_top/u_stim_config/bram_din[27]} {u_pl_top/u_stim_config/bram_din[28]} {u_pl_top/u_stim_config/bram_din[29]} {u_pl_top/u_stim_config/bram_din[30]} {u_pl_top/u_stim_config/bram_din[31]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 4 [get_debug_ports u_ila_0/probe27]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
|
connect_debug_port u_ila_0/probe27 [get_nets [list {u_pl_top/u_stim_config/bram_we[0]} {u_pl_top/u_stim_config/bram_we[1]} {u_pl_top/u_stim_config/bram_we[2]} {u_pl_top/u_stim_config/bram_we[3]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 13 [get_debug_ports u_ila_0/probe28]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
|
connect_debug_port u_ila_0/probe28 [get_nets [list {u_pl_top/u_stim_config/bram_addr[0]} {u_pl_top/u_stim_config/bram_addr[1]} {u_pl_top/u_stim_config/bram_addr[2]} {u_pl_top/u_stim_config/bram_addr[3]} {u_pl_top/u_stim_config/bram_addr[4]} {u_pl_top/u_stim_config/bram_addr[5]} {u_pl_top/u_stim_config/bram_addr[6]} {u_pl_top/u_stim_config/bram_addr[7]} {u_pl_top/u_stim_config/bram_addr[8]} {u_pl_top/u_stim_config/bram_addr[9]} {u_pl_top/u_stim_config/bram_addr[10]} {u_pl_top/u_stim_config/bram_addr[11]} {u_pl_top/u_stim_config/bram_addr[12]} ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
|
connect_debug_port u_ila_0/probe29 [get_nets [list u_pl_top/axi_i_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
|
connect_debug_port u_ila_0/probe30 [get_nets [list u_pl_top/axi_i_wr ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
|
connect_debug_port u_ila_0/probe31 [get_nets [list u_pl_top/axis_eeg24_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
|
connect_debug_port u_ila_0/probe32 [get_nets [list u_pl_top/axis_eeg24_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
|
connect_debug_port u_ila_0/probe33 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
|
connect_debug_port u_ila_0/probe34 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_eeg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
|
connect_debug_port u_ila_0/probe35 [get_nets [list u_pl_top/axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
|
connect_debug_port u_ila_0/probe36 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
|
connect_debug_port u_ila_0/probe37 [get_nets [list u_pl_top/axis_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
|
connect_debug_port u_ila_0/probe38 [get_nets [list u_pl_top/axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
|
connect_debug_port u_ila_0/probe39 [get_nets [list u_pl_top/u_eeg_emg_upload/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
|
connect_debug_port u_ila_0/probe40 [get_nets [list u_pl_top/axis_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
|
connect_debug_port u_ila_0/probe41 [get_nets [list u_pl_top/u_stim_config/bram_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
|
connect_debug_port u_ila_0/probe42 [get_nets [list u_pl_top/u_stim_config/bram_rd_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
|
connect_debug_port u_ila_0/probe43 [get_nets [list u_pl_top/u_stim_config/bram_wr_valid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
|
connect_debug_port u_ila_0/probe44 [get_nets [list u_pl_top/u_eeg_emg_upload/crc_vld ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
|
connect_debug_port u_ila_0/probe45 [get_nets [list u_pl_top/u_eeg_emg_upload/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
|
connect_debug_port u_ila_0/probe46 [get_nets [list u_pl_top/u_stim_config/diff_pkt_data_sel ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
|
connect_debug_port u_ila_0/probe47 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
|
connect_debug_port u_ila_0/probe48 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tlast_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
|
connect_debug_port u_ila_0/probe49 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
|
connect_debug_port u_ila_0/probe50 [get_nets [list u_pl_top/u_eeg_emg_upload/eeg_emg_tvalid_tmp ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
|
connect_debug_port u_ila_0/probe51 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
|
connect_debug_port u_ila_0/probe52 [get_nets [list u_pl_top/u_eeg_emg_upload/fifo_emg_rd_en_dly ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
|
connect_debug_port u_ila_0/probe53 [get_nets [list u_pl_top/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
|
connect_debug_port u_ila_0/probe54 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
|
connect_debug_port u_ila_0/probe55 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
|
connect_debug_port u_ila_0/probe56 [get_nets [list u_pl_top/m_axis_eeg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
|
connect_debug_port u_ila_0/probe57 [get_nets [list u_pl_top/m_axis_emg_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
|
connect_debug_port u_ila_0/probe58 [get_nets [list u_pl_top/u_eeg_emg_upload/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
|
connect_debug_port u_ila_0/probe59 [get_nets [list u_pl_top/m_axis_emg_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
|
connect_debug_port u_ila_0/probe60 [get_nets [list u_pl_top/m_axis_record_tfull ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
|
connect_debug_port u_ila_0/probe61 [get_nets [list u_pl_top/m_axis_record_tlast ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
|
connect_debug_port u_ila_0/probe62 [get_nets [list u_pl_top/m_axis_record_tready ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
|
connect_debug_port u_ila_0/probe63 [get_nets [list u_pl_top/m_axis_record_tvalid ]]
|
|
create_debug_port u_ila_0 probe
|
|
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
|
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
|
connect_debug_port u_ila_0/probe64 [get_nets [list mux_pwr_en_OBUF ]]
|
|
reset_run synth_1
|
|
save_constraints -force
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 20
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
|
|
[Thu Aug 20 13:55:28 2026] Launched synth_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/synth_1/runme.log
|
|
[Thu Aug 20 13:55:28 2026] Launched impl_1...
|
|
Run output will be captured here: D:/Project/spinal_stim/pl/spinal_stim_v3/c64_pro.runs/impl_1/runme.log
|
|
write_hw_platform -fixed -include_bit -force -file D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa
|
|
INFO: [Project 1-1918] Creating Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa ...
|
|
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
|
|
INFO: [Project 1-1941] Successfully created Hardware Platform: D:/Project/spinal_stim/pl/spinal_stim_v3/c64pro_top.xsa
|
|
write_hw_platform: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 5381.410 ; gain = 41.668
|
|
exit
|
|
INFO: [Common 17-206] Exiting Vivado at Mon Aug 31 10:52:51 2026...
|